Showing papers on "Amplifier published in 2008"
16 Jan 2008
TL;DR: The latest developments of the GaN HEMT technologies, including material growth, processing technologies, device epitaxial structures and MMIC designs, are reviewed to achieve the state-of-the-art microwave and millimeter-wave performance.
Abstract: The rapid development of the RF power electronics requires the introduction of wide bandgap material due to its potential in high output power density, high operation voltage and high input impedance GaN-based RF power devices have made substantial progresses in the last decade This paper attempts to review the latest developments of the GaN HEMT technologies, including material growth, processing technologies, device epitaxial structures and MMIC designs, to achieve the state-of-the-art microwave and millimeter-wave performance The reliability and manufacturing challenges are also discussed
1,503 citations
TL;DR: It is shown that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDs(V GS) relation at practical gain values.
Abstract: An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDS(VGS) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm2.
579 citations
Book•
01 Jan 2008
TL;DR: In this article, the authors compare MOST and Bipolar transistor models, including Amplifiers, Source followers, and Cascodes, with differentially voltage and current amplifiers.
Abstract: Comparison of MOST and Bipolar transistor models.- Amplifiers, Source followers & Cascodes.- Differential Voltage and Current amplifiers.- Noise performance of elementary transistor stages.- Stability of Operational amplifiers.- Systematic Design of Operational Amplifiers.- Important opamp configurations.- Fully-differential amplifiers.- Design of Multistage Operational amplifiers.- Current-input Operational Amplifiers.- Rail-to-rail input and output amplifiers.- Class AB and driver amplifiers.- Feedback Voltage and Transconductance Amplifiers.- Feedback Transimpedance and Current Amplifiers.- Offset and CMRR: Random and systematic.- Bandgap and current reference circuits.- Switched-capacitor filters.- Distortion in elementary transistor circuits.- Continuous-time filters.- CMOS ADC and DAC principles.- Low-power Sigma-Delta AD converters.- Design of crystal oscillators.- Low-noise amplifiers.- Coupling effects in Mixed analog-digital ICs.
563 citations
TL;DR: The CP-FTMW spectrometer produces an equal sensitivity spectrum with a factor of 40 reduction in measurement time and a reduction in sample consumption by a factors of 20, and displays good intensity accuracy for both sample number density and rotational transition moment.
Abstract: Designs for a broadband chirped pulse Fourier transform microwave (CP-FTMW) spectrometer are presented. The spectrometer is capable of measuring the 7-18 GHz region of a rotational spectrum in a single data acquisition. One design uses a 4.2 Gsampless arbitrary waveform generator (AWG) to produce a 1 mus duration chirped pulse with a linear frequency sweep of 1.375 GHz. This pulse is sent through a microwave circuit to multiply the bandwidth of the pulse by a factor of 8 and upconvert it to the 7.5-18.5 GHz range. The chirped pulse is amplified by a traveling wave tube amplifier and broadcast inside the spectrometer by using a double ridge standard gain horn antenna. The broadband molecular free induction decay (FID) is received by a second horn antenna, downconverted, and digitized by a 40 Gsampless (12 GHz hardware bandwidth) digital oscilloscope. The second design uses a simplified pulse generation and FID detection scheme, employing current state-of-the-art high-speed digital electronics. In this spectrometer, a chirped pulse with 12 GHz of bandwidth is directly generated by using a 20 Gsampless AWG and upconverted in a single step with an ultrabroadband mixer. The amplified molecular emission is directly detected by using a 50 Gsampless digital oscilloscope with 18 GHz bandwidth. In both designs, fast Fourier transform of the FID produces the frequency domain rotational spectrum in the 7-18 GHz range. The performance of the CP-FTMW spectrometer is compared to a Balle-Flygare-type cavity-FTMW spectrometer. The CP-FTMW spectrometer produces an equal sensitivity spectrum with a factor of 40 reduction in measurement time and a reduction in sample consumption by a factor of 20. The CP-FTMW spectrometer also displays good intensity accuracy for both sample number density and rotational transition moment. Strategies to reduce the CP-FTMW measurement time by another factor of 90 while simultaneously reducing the sample consumption by a factor of 30 are demonstrated.
493 citations
TL;DR: In this paper, a Josephson parametric amplifier consisting of a superconducting coplanar-waveguide resonator terminated by a dc super-conducting quantum interference device (SQUID) is presented.
Abstract: We have developed a Josephson parametric amplifier comprising a superconducting coplanar-waveguide resonator terminated by a dc superconducting quantum interference device (SQUID). An external field (the pump, ∼20 GHz) modulates the flux threading of the dc SQUID and, therefore, the resonant frequency of the cavity field (the signal, ∼10 GHz), which leads to the parametric signal amplification. We operated the amplifier at different band centers and observed amplification (17 dB at maximum) and deamplification depending on the relative phase between the pump and the signal. The noise temperature is estimated to be less than 0.87 K.
410 citations
17 Jun 2008
TL;DR: Integrated circuits and design techniques are presented that address the twin problems of neural signal amplification and data reduction for this severely size- and power-limited application.
Abstract: The ability to monitor the simultaneous electrical activity of multiple neurons in the brain enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature multielectrode neural recording arrays with integrated electronics have revealed significant circuit design challenges. Weak neural signals must be amplified and filtered using low-noise circuits placed close to the electrodes themselves, but power dissipation must strictly be limited to prevent tissue damage due to local heating. In modern recording systems with 100 or more electrodes, raw data rates of 15 Mb/s or more are easily produced. Micropower wireless telemetry circuits cannot transmit information at such high rates, so data reduction must be performed in the implanted device. In this paper, we present integrated circuits and design techniques that address the twin problems of neural signal amplification and data reduction for this severely size- and power-limited application.
309 citations
Patent•
27 Feb 2008TL;DR: In this article, active transmitter leakage cancellation techniques for reducing transmitter leakage in a frequency-duplexing radio transceiver are disclosed, for reducing the linearity requirements for low-noise amplifier and mixer circuits, potentially reducing transceiver cost as well as complexity.
Abstract: Active transmitter leakage cancellation techniques are disclosed, for reducing transmitter leakage in a frequency-duplexing radio transceiver. Reducing transmitter leakage to the receiver path of a duplex transceiver eases the linearity requirements for low-noise amplifier and mixer circuits, potentially reducing transceiver cost as well as complexity. In an exemplary method, a radio-frequency (RF) cancellation signal is generated from a transmitter signal, and the RF cancellation signal is combined with a received RF signal to obtain a combined RF signal comprising a residual transmitter leakage component. The residual transmitter leakage component of the combined RF signal is converted, using, e.g., a frequency mixer, to obtain a down-converted signal at baseband or at an intermediate frequency. A magnitude of the residual transmitter leakage component is detected from the down-converted signal, and used to adjust the phase or amplitude of the RF cancellation signal, or both, to reduce the residual transmitter leakage component.
287 citations
TL;DR: In this article, an efficient open-loop digital predistorter (DPD) derived from the dynamic deviation reduction-based Volterra series that allows compensation for both nonlinear distortion and memory effects induced by RF power amplifiers in wireless transmitters is proposed.
Abstract: In this paper, we propose an efficient open-loop digital predistorter (DPD) derived from the dynamic deviation reduction-based Volterra series that allows compensation for both nonlinear distortion and memory effects induced by RF power amplifiers in wireless transmitters. In this approach, the parameters of the predistorter can be directly extracted from an offline system identification process. This eliminates the usual requirement for a closed-loop real-time parameter adaptation, which dramatically reduces the implementation complexity of the system. It is shown that a further reduction in system complexity can be achieved by applying under-sampling theory in the model extraction and utilizing parameter interpolation in the DPD implementation. Experimental results show that by utilizing this technique with only a small number of parameters, nonlinear distortion induced by the PA can be significantly reduced, as evaluated by both adjacent channel power ratio reduction and normalized root mean square error improvement. A comparison with a memoryless polynomial function based predistorter and an analysis of the impact of decresting are also presented.
266 citations
TL;DR: This work fabricated nanotube transistor radios, in which SWNT devices provide all of the key functions, including resonant antennas, fixed RF amplifiers, RF mixers, and audio amplifiers.
Abstract: The potential to exploit single-walled carbon nanotubes (SWNTs) in advanced electronics represents a continuing, major source of interest in these materials. However, scalable integration of SWNTs into circuits is challenging because of difficulties in controlling the geometries, spatial positions, and electronic properties of individual tubes. We have implemented solutions to some of these challenges to yield radio frequency (RF) SWNT analog electronic devices, such as narrow band amplifiers operating in the VHF frequency band with power gains as high as 14 dB. As a demonstration, we fabricated nanotube transistor radios, in which SWNT devices provide all of the key functions, including resonant antennas, fixed RF amplifiers, RF mixers, and audio amplifiers. These results represent important first steps to practical implementation of SWNTs in high-speed analog circuits. Comparison studies indicate certain performance advantages over silicon and capabilities that complement those in existing compound semiconductor technologies.
227 citations
Patent•
19 Dec 2008
TL;DR: In this paper, the authors describe classes of robust fiber laser systems usable as pulse sources for Nd: or Yb: based regenerative amplifiers intended for industrial settings, and modifies adapts and incorporates several recent advances in FCPA systems to use as the input source for this new class of regenerative amplifier.
Abstract: The invention describes classes of robust fiber laser systems usable as pulse sources for Nd: or Yb: based regenerative amplifiers intended for industrial settings. The invention modifies adapts and incorporates several recent advances in FCPA systems to use as the input source for this new class of regenerative amplifier.
208 citations
Patent•
29 Jan 2008TL;DR: In this article, an envelope tracking (ET) method for controlling the delivery of power to radio frequency power amplifiers (RFPAs) is described. But the system is not suitable for the use of a power amplifier.
Abstract: Envelope tracking (ET) methods and systems for controlling the delivery of power to radio frequency power amplifiers (RFPAs). An exemplary ET system includes an RFPA and a wide bandwidth capable and power efficient envelope modulator that includes a first power supplying apparatus and a second power supplying apparatus. The first power supplying apparatus includes a switch-mode converter and a regulator. The first mode converter is operable to dynamically step down a fixed power supply voltage according to amplitude variations in an envelope signal received by the regulator, and use the resulting dynamic power supply signal to power the regulator. The second power supplying apparatus is connected in parallel with the first power supplying apparatus. Depending on a power of an output signal to be generated at an output of the power amplifier, power is supplied to the power amplifier from either or both of the first and second power supplying apparatuses.
Patent•
27 Jun 2008
TL;DR: In this paper, the power efficiency improvement mechanism leverages the high efficiency of a switched-mode power supply (SMPS) that supplies the high DC current to the transmitter's power amplifier, while compensating for its limitations using predistortion.
Abstract: A novel apparatus and method of improving the power efficiency of a digital transmitter for non-constant-amplitude modulation schemes. The power efficiency improvement mechanism of the invention leverages the high efficiency of a switched-mode power supply (SMPS) that supplies the high DC current to the transmitter's power amplifier, while compensating for its limitations using predistortion. The predistortion may be achieved using any suitable technique such as digital signal processing, hardware techniques, etc. A switched mode power supply (i.e. switching regulator) is used to provide a slow form (i.e. reduced bandwidth) of envelope tracking (based on a narrower bandwidth distorted version of the envelope waveform) such that the switching regulator can use a lower switching rate corresponding to the lower bandwidth, thereby obtaining high efficiency in the switching regulator. The resulting AM-AM and AM-PM distortions in the power amplifier are compensated through predistortion of the digital amplitude modulating signal which dictates the envelope at the PA input. Similarly, the phase modulation is also compensated prior to the PA, such that once it undergoes the distortion in the PA, the end result is sufficiently close to the desired phase.
TL;DR: In this paper, a three-way Doherty 100-W GaN power amplifier at 2.14 GHz was presented, where mixed-signal techniques were utilized for uncompromised control of the amplifier stages to optimize efficiency, as well as linearity.
Abstract: A three-way Doherty 100-W GaN base-station power amplifier at 2.14 GHz is presented. Simple, but accurate design equations for the output power combiner of the amplifier are introduced. Mixed-signal techniques are utilized for uncompromised control of the amplifier stages to optimize efficiency, as well as linearity. The combination of the above techniques resulted in an unprecedented high efficiency over a 12-dB power backoff range, facilitating a record high power-added efficiency for a wideband code division multiple access test signal with high crest factor, while meeting all the spectral requirements for Universal Mobile Telecommunications System base stations.
TL;DR: This paper presents a new approach for power amplifier design using deep submicron CMOS technologies and a transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers.
Abstract: This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.
TL;DR: It is demonstrated that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).
Abstract: The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).
Patent•
04 Jan 2008
TL;DR: A circuit for use with a power amplifier that amplifies an input signal is defined in this paper, where an amplitude correction circuit and an open-loop switching regulator are used to generate a corrected envelope signal from an input envelope signal.
Abstract: A circuit for use with a power amplifier that amplifies an input signal The circuit may comprise an amplitude correction circuit and an open-loop switching regulator The amplitude correction circuit may be configured to generate a corrected envelope signal from an input envelope signal that represents an envelope of the input signal The open-loop switching regulator may be connected to the amplitude correction circuit and may be for powering the power amplifier based on the corrected envelope signal According to various embodiments, the corrected envelope signal generated by the amplitude correction circuit is a function of the input envelope signal and an error voltage of the open-loop switching regulator
Book•
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01 Jan 2008
TL;DR: In this paper, the authors present a block diagram of RF Power Amplifiers and demonstrate the operation of different classes of power amplifiers, including ZVS and ZDS operation of Class E Amplifier.
Abstract: Preface About the Author List of Symbols 1. Introduction 1.1 Block Diagram of RF Power Amplifiers 1.2 Classes of Operation of RF Power Amplifiers 1.3 Parameters of RF Power Amplifiers 1.4 Conditions for 100% Efficiency of Power Amplifiers 1.5 Conditions for Nonzero Output Power at 100% Efficiency of Power Amplifiers 1.6 Output Power of Class E ZVS Amplifier 1.7 Class E ZCS Amplifier 1.8 Propagation of Electromagnetic Waves 1.9 Frequency Spectrum 1.10 Duplexing 1.11 Multiple-access Techniques 1.12 Nonlinear Distortion in Transmitters 1.13 Harmonics of Carrier Frequency 1.14 Intermodulation 1.15 Dynamic Range of Power Amplifiers 1.16 Analog Modulation 1.17 Digital Modulation 1.18 Radars 1.19 Radio-frequency Identification 1.20 Summary 1.21 References 1.22 Review Questions 1.23 Problems 2. Class A RF Power Amplifier 2.1 Introduction 2.2 Circuit of Class A RF Power Amplifier 2.3 Power MOSFET Characteristics 2.4 Waveforms of Class A RF Amplifier 2.5 Parameters of Class A RF Power Amplifier 2.6 Parallel-resonant Circuit 2.7 Power Losses and Efficiency of Parallel Resonant Circuit 2.8 Impedance Matching Circuits 2.9 Class A RF Linear Amplifier 2.10 Summary 2.11 References 2.12 Review Questions 2.13 Problems 3. Class AB, B, and C RF Power Amplifiers 3.1 Introduction 3.2 Class B RF Power Amplifier 3.3 Class AB and C RF Power Amplifiers 3.4 Push-pull Complementary Class AB, B, and C RF Power Amplifiers 3.5 Transformer-coupled Class B Push-pull Amplifier 3.6 Class AB, B, and C Amplifiers of Variable-envelope Signals 3.7 Summary 3.8 References 3.9 Review Questions 3.10 Problems 4. Class D RF Power Amplifier 4.1 Introduction 4.2 Circuit Description 4.3 Principle of Operation 4.4 Topologies of Class D Voltage-source RF Power Amplifiers 4.5 Analysis 4.6 Voltage Transfer Function 4.7 Bandwidth of Class D Amplifier 4.8 Efficiency of Half-bridge Class D Power Amplifier 4.9 Design Example 4.10 Class D RF Power Amplifier with Amplitude Modulation 4.11 Transformer-coupled Push-pull Class D Voltage-switching RF Power Amplifier 4.12 Class D Full-bridge RF Power Amplifier 4.13 Phase Control of Full-bridge Class D Power Amplifier 4.14 Class D Current-switching RF Power Amplifier 4.15 Transformer-coupled Push-pull Class D Current-switching RF Power Amplifier 4.16 Bridge Class D Current-switching RF Power Amplifier 4.17 Summary 4.18 References 4.19 Review Questions 4.20 Problems 5. Class E RF Zero-voltage-switching RF Power Amplifier 5.1 Introduction 5.2 Circuit Description 5.3 Circuit Operation 5.4 ZVS and ZDS Operation of Class E Amplifier 5.5 Suboptimum Operation 5.6 Analysis 5.7 Maximum Operating Frequency 5.8 Choke Inductance 5.9 Summary of Parameters at D = 0 . 5 5.10 Efficiency 5.11 Design of Basic Class E Amplifier 5.12 Impedance Matching Resonant Circuits 5.13 Push-pull Class E ZVS RF Amplifier 5.14 Class E ZVS RF Power Amplifier with Finite DC-feed Inductance 5.15 Class E ZVS Amplifier with Parallel-series Resonant Circuit 5.16 Class E ZVS Amplifier with Nonsinusoidal Output Voltage 5.17 Class E ZVS Power Amplifier with Parallel Resonant Circuit 5.18 Amplitude Modulation of Class E ZVS RF Power Amplifier 5.19 Summary 5.20 References 5.21 Review Questions 5.22 Problems 6. Class E Zero-current-switching RF Power Amplifier 6.1 Introduction 6.2 Circuit Description 6.3 Principle of Operation 6.4 Analysis 6.5 Power Relationships 6.6 Element Values of Load Network 6.7 Design Example 6.8 Summary 6.9 References 6.10 Review Questions 6.11 Problems 7. Class DE RF Power Amplifier 7.1 Introduction 7.2 Analysis of Class DE RF Power Amplifier 7.3 Components 7.4 Device Stresses 7.5 Design Equations 7.6 Maximum Operating Frequency 7.7 Class DE Amplifier with Only One Shunt Capacitor 7.8 Components 7.9 Cancellation of Nonlinearities of Transistor Output Capacitances 7.10 Summary 7.11 References 7.12 Review Questions 7.13 Problems 8. Class F RF Power Amplifier 8.1 Introduction 8.2 Class F RF Power Amplifier with Third Harmonic 8.3 Class F RF Power Amplifier with Third and Fifth Harmonics 8.4 Class F RF Power Amplifier with Third, Fifth, and Seventh Harmonics 8.5 Class F RF Power Amplifier with Parallel-resonant Circuit and Quarter-wavelength Transmission Line 8.6 Class F RF Power Amplifier with Second Harmonic 8.7 Class F RF Power Amplifier with Second and Fourth Harmonics 8.8 Class F RF Power Amplifier with Second, Fourth, and Sixth Harmonics 8.9 Class F RF Power Amplifier with Series-resonant Circuit and Quarter-wavelength Transmission Line 8.10 Summary 8.11 References 8.12 Review Questions 8.13 Problems 9. Linearization and Efficiency Improvement of RF Power Amplifiers 9.1 Introduction 9.2 Predistortion 9.3 Feedforward Linearization Technique 9.4 Negative Feedback Linearization Technique 9.5 Envelope Elimination and Restoration 9.6 Envelope Tracking 9.7 The Doherty Amplifier 9.8 Outphasing Power Amplifier 9.9 Summary 9.10 References 9.11 Review Questions 9.12 Problems 10. Integrated Inductors 10.1 Introduction 10.2 Skin Effect 10.3 Resistance of Rectangular Trace 10.4 Inductance of Straight Rectangular Trace 10.5 Meander Inductors 10.6 Inductance of Straight Round Conductor 10.7 Inductance of Circular Round Wire Loop 10.8 Inductance of Two-parallel Wire Loop 10.9 Inductance of Rectangle of Round Wire 10.10 Inductance of Polygon Round Wire Loop 10.11 Bondwire Inductors 10.12 Single-turn Planar Inductors 10.13 Inductance of Planar Square Loop 10.14 Planar Spiral Inductors 10.15 Multimetal Spiral Inductors 10.16 Planar Transformers 10.17 MEMS Inductors 10.18 Inductance of Coaxial Cable 10.19 Inductance of Two-wire Transmission Line 10.20 Eddy Currents in Integrated Inductors 10.21 Model of RF Integrated Inductors 10.22 PCB Integrated Inductors 10.23 Summary 10.24 References 10.25 Review Questions 10.26 Problems Appendices Appendix A SPICE Model of Power MOSFETs Appendix B Introduction to SPICE Appendix C Introduction to MATLAB Answers to Problems Index
TL;DR: In this paper, a piecewise Volterra model based on a vector threshold decomposition technique was introduced to compensate the distortion induced by power amplifiers by employing conventional digital predistortion techniques.
Abstract: Due to dynamic changes of supply voltage, envelope-tracking (ET) power amplifiers (PAs) exhibit very distinct characteristics in different power regions. It is very difficult to compensate the distortion induced by these amplifiers by employing conventional digital predistortion techniques. In this paper, by introducing a new piecewise Volterra model based on a vector threshold decomposition technique, we first set several thresholds in the input power level according to the PA characteristics, and decompose the input complex envelope signal into several sub-signals by using these thresholds. We then process each sub-signal separately by employing the dynamic deviation reduction-based Volterra series, and finally recombine them together to produce the predistorted output. Experimental results show that by using this new decomposed piecewise digital predistorter model, the distinct characteristics of the ET system at different signal power levels can be accurately modeled, and thus, the distortion, including both static nonlinearities and memory effects, caused by the amplifier nonlinear behavior can be effectively compensated.
TL;DR: By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain and shows very high figure of merit among the state-of-the-art sub-l-V modulators.
Abstract: A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.
TL;DR: This work uses a smaller noise reduction inductor compared with the conventional inductor based technique to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA.
Abstract: A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.
01 Feb 2008
TL;DR: A low-voltage fast transient-response LDO regulator using an inexpensive 0.35 mum CMOS process is presented in this paper, which features a current-efficient adaptively biased regulation scheme using a low- voltage high-speed super current mirror and does not require a compensation capacitor.
Abstract: Portable applications often need multiple voltages controlled by a power management IC to power up many functional blocks A switching pre-regulator is usually followed by a low dropout (LDO) regulator to provide a regulated power source for noise-sensitive blocks The LDO regulator has to be stable for all load conditions and frequency compensation is usually needed to stabilize the regulation loop The output voltage droop due to rapid and large load changes could be minimized with a fast regulation loop, such that functional blocks powered by the same LDO regulator would have low crosstalk noise A low-voltage fast transient-response LDO regulator using an inexpensive 035 mum CMOS process is presented in this paper It features a current-efficient adaptively biased regulation scheme using a low-voltage high-speed super current mirror and does not require a compensation capacitor It is stabilized by a low-cost low-ESR ceramic filter capacitor of 1 muF The adaptively biased error amplifier EA drives a small transconductance cell to modulate the output current through a transient-enhanced super current-mirror (SCM)
TL;DR: These effects and the resulting amplitude envelope delays and distortion of waveforms recorded through a commercial data acquisition system and a range of tungsten microelectrodes are reported.
22 Apr 2008
TL;DR: A fully integrated 5.8 GHz Class AB linear power amplifier in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network to achieve maximum output power and low insertion loss over the bandwidth of interest.
Abstract: A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.
22 Apr 2008
TL;DR: Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented, showing the parasitic resistance and the turn ratio as the limiting factor of power combining.
Abstract: Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.
TL;DR: In this paper, a concurrent dual-band high-efficiency harmonic tuned (HT) power amplifiers (PAs) were proposed based on a methodology developed to design multifrequency passive matching networks, which allows concurrent operability.
Abstract: In this paper, a novel technique to design concurrent dual-band high-efficiency harmonic tuned (HT) power amplifiers (PAs) is presented. The proposed approach is based on a methodology developed to design multifrequency passive matching networks, which allows concurrent operability. The network design criterion is heavily investigated and later generalized both from the theoretical and practical point of view. The design, realization, and the complete characterization of a concurrent dual-band high-efficiency HT PA is finally described. A 1-mm gate periphery GaN HEMT device was used for the design and realization of the PA operating concurrently at 2.45 and 3.3 GHz. The measurement results have shown 53% and 46% drain efficiency at 33- and 32.5-dBm output power in the two targeted bands if operated in continuous wave single mode. In concurrent mode, 35% average efficiency was achieved with two simultaneously applied orthogonal frequency-division multiplexing signals.
TL;DR: A CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements and suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope is presented.
Abstract: This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm2 , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.
Patent•
04 Aug 2008TL;DR: In this paper, an amplifier circuit consisting of an input, a power amplifier, and a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switch power supply.
Abstract: There is provided an amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.
TL;DR: A low Terahertz frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency by linear superposition (LS) technique.
Abstract: A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.
TL;DR: The design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS, including an on-chip spiral balun, and the transition from CPW to the balun and transistor noise parameter measurement results at V-band are presented.
Abstract: We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at +6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 mm2. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of +7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and +5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with -19 dBm of 1-dB output compression point.
Patent•
11 Nov 2008
TL;DR: In this paper, a power amplifier controller adjusts the supply voltage so that distortion in an RF output signal corresponds to a predetermined limit, and the deviation signal drops below the distortion level control signal.
Abstract: A power amplifier controller for adjusting a supply voltage to a power amplifier. The power amplifier controller adjusts the supply voltage so that distortion in an RF output signal corresponds to a predetermined limit. An amplitude error signal is generated by the power amplifier controller which represents a difference between an RF output signal and an attenuated RF output signal. The AC components of the amplitude error signal are processed to generate a deviation signal that represents the distortion in the RF output signal. The supply voltage to the power amplifier is increased when the deviation signal exceeds a distortion level control signal, and decreased when the deviation signal drops below the distortion level control signal.