Topic

# Analog-to-digital converter

About: Analog-to-digital converter is a research topic. Over the lifetime, 7858 publications have been published within this topic receiving 78030 citations. The topic is also known as: ADC.

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HRL Laboratories

^{1}TL;DR: The state-of-the-art of ADCs is surveyed, including experimental converters and commercially available parts, and the distribution of resolution versus sampling rate provides insight into ADC performance limitations.

Abstract: Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from /spl sim/2 Ms/s to /spl sim/4 giga samples per second (Gs/s), resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only /spl sim/1.5 bits for any given sampling frequency over the last six-eight years.

2,220 citations

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TL;DR: In this paper, the authors proposed a novel digital carrier recovery algorithm for arbitrary M-ary quadrature amplitude modulation (M-QAM) constellations in an intradyne coherent optical receiver.

Abstract: This paper presents a novel digital feedforward carrier recovery algorithm for arbitrary M-ary quadrature amplitude modulation (M-QAM) constellations in an intradyne coherent optical receiver. The approach does not contain any feedback loop and is therefore highly tolerant against laser phase noise. This is crucial, especially for higher order QAM constellations, which inherently have a smaller phase noise tolerance due to the lower spacing between adjacent constellation points. In addition to the mathematical description of the proposed carrier recovery algorithm also a possible hardware-efficient implementation in a parallelized system is presented and the performance of the algorithm is evaluated by Monte Carlo simulations for square 4-QAM (QPSK), 16-QAM, 64-QAM, and 256-QAM. For the simulations ASE noise and laser phase noise are considered as well as analog-to-digital converter (ADC) and internal resolution effects. For a 1 dB penalty at BER = 10-3, linewidth times symbol duration products of 4.1 x 10-4 (4-QAM), 1.4 x 10-4 (16-QAM), 4.0 x 10-5 (64-QAM) and 8.0 x 10-6 (256-QAM) are tolerable.

976 citations

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TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.

Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

966 citations

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Bell Labs

^{1}TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.

Abstract: A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

570 citations

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TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.

Abstract: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.

432 citations