Showing papers on "AND gate published in 1968"

Multifrequency tone detector

Abstract: 1,221,890. Telephone exchange receivers. WESTERN ELECTRIC CO. Inc. 2 Dec., 1969 [5 Dec., 1968], No. 58680/69. Heading H4K. [Also in Divisions G4-G6] A tone detector determines which one of a number of signal frequencies is present by counting the number of clock pulses between zero crossings of the received waveform, decoding AND-gates connected to the counter indicating acceptable upper and lower counts for each signal frequency and thereby providing for each frequency a recognition bandwidth to allow for the fact that the signals may originate from different sources at different times and be subject to slight variation. In the 1-out-of-4 multifrequency detector illustrated the received sinusoidal signal is squared and positive or negative going zero-crossings are signalled as spikes to drive a synch. circuit 13 which replaces an input spike with the next occurring clock pulse. The first received zero-crossing spike resets output bi-stables 24 to 27 and, after a one-clock pulse delay introduced by circuit 21, it resets the counter 22 and the recognition bandwidth bi-stables 14 to 17. If the count from this reset point reaches the lower limit 179 of the recognition band of the highest expected frequency an AND gate decoder sets bi-stable 14. If the count proceeds beyond the upper limit 189 of the recognition band an AND gate decoder resets the bi-stable 14. Bi-stables 15, 16 and 17 are similarly set and reset as the count passes through the recognition bands of the lower frequencies. If, as will occur with the reception of one of the four frequencies, the next zero crossing spike occurs when the count lies within a recognition band the operation of gates such as 18, 19 transfers the set state of one of the bi-stables 14 to 17 to the corresponding output bi-stable 24 to 27. Should the count procee. beyond the last range a gate 29 stops the count to prevent recycling and false operation in response to harmonics. Two such receivers may be used in parallel, one for 1-out-of-4 high frequencies, the other for 1-out-of-4 low frequencies, the two sets of frequencies being separated by a filter and the two receivers differing only to the extent of working with different clock frequencies.

Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements

Abstract: —In an earlier paper, Unger showed that any normal mode flow table can be realized by an asynchronous sequential circuit without inserted delays in the feedback paths if and only if the flow table contains no essential hazards. No restrictions were placed on the relative magnitudes of line and gate delays. In this paper, we show that if the line delays are less than the minimum gate delay in the circuit, any normal mode sequential function can be realized without inserted delays. It is also shown that a weaker line delay assumption is sufficient. Two procedures for realizing asynchronous sequential circuits without inserted delays are presented.

System for confirming the validity of repetitively sampled digital data

Abstract: 1,260,620. Testing signals. NORTHROP CORP. 28 May, 1970, No. 25845/70. Heading G4H. The validity of a plurality of binary data signals, each on a separate input line 16a-16n is confirmed by testing their duration, in a circuit comprising a sampling gate 20a-20n for each input, a counter 13 enabling the gates in turn, a counter 14 for locking on to a selected one of the inputs, counter 14 advancing in step with counter 13 but being offset from it, a gate 30 controlled by counter 14 repeatedly to sample the selected input and a counter 40 counting successive output pulses from gate 30, each indicating that the selected input has lasted for one cycle of counter 13, counter 40 giving a confirmation signal after a given number of pulses. Counter 13 cycles continuously but counter 14 counts up to "n" and stops in this condition. If an input is present on line 16b gate 20b gives an output when counter 13 is on 2. This output, passing through or gate 27 and gate 30 resets counter 14 so that it can count pulses from generator 12. It is displaced by a count of 2 from counter 13. The signal from gate 30 also passes to counter 40. When counter 13 is next on 2, counter 14 is again on "n" and if the signal is still present on input 16b the output from gate 20b again passes through gates 27 and 30 to step counter 40. When this counter reaches a count of "n" the next output from gate 30 passes through gate 50 to enable output gates 54a-54n passing the inputs on lines 16a-16n as confirmed The confirmation signal resets counters 14 and 40. If the input on line 16b disappears before counter 40 reaches "n" the inverted output from gate 27 enables gate and resets counter 40. After confirming input 16b counter 14 then locks on to the next input carrying a signal.

Dependence of the characteristics of MOS-transistors on the substrate resistivity

Abstract: The d.c. and small-signal a.c. characteristics of MOS-transistors are studied with particular reference to their dependence on the substrate resistivity. Useful approximate expressions are derived for the drain current and for the gate and substrate transconductances. Expressions are also derived for the self and mutual capacitances associated with the gate and the substrate terminals. Apart from increasing the threshold voltage, an increase in the substrate impurity density is found to reduce the saturation drain current and the gate transconductance but to enhance the substrate transconductance. The total transconductance associated with the gate and substrate and the gate transconductance to drain current ratio are, however, shown to be independent of the substrate resistivity. A heavily doped substrate device is thus shown to be superior to a lightly doped substrate device with regard to the total transconductance to drain current ratio. Results of practical measurements on several n -channel MOS-transistors are presented which support the general validity of the theory and the proposed small-signal equivalent circuit. A simple method is suggested for the determination of the substrate control parameter, A , which is related to the substrate impurity density and gate oxide layer capacitance.

Fluidic control circuit for presses

Abstract: 1,216,435. Fluid logic and switching circuits. E. W. BLISS CO. April 3, 1969 [April 10, 1968], No. 17696/69. Heading F1P. A fluidic control circuit for alternatively actuating a clutch mechanism and a brake mechanism of a press comprises a gate 9NOR having respective output lines 01, 02 connected to the clutch and brake mechanisms and having an input line C 1 connected to the output of a first AND gate 50 having two or more inputs C 2 , C 1 the former being fed by a feedback loop through 64 and 7NOR from the output O 2 of said AND gate 50 (8NOR) and the latter input C 1 being provided with an input signal whilst means 64 is provided for interrupting the signal to at least one input C 2 of gate 50. The press which is crankshaft driven may run continuously or on a single stroke basis or by inching through a 360 degree crank rotation. It is preferably stopped at the top of its stroke but at any position in an emergency. To start the press a momentary C 2 input at 9NOR gate is provided by outlet 01 of 1 AND gate 24 which outlet is obtained by momentarily pressing spring-returned valves 16, 18 in parallel branches 20, 20a of the main air supply line thereby providing a momentary C 2 input at gate 24; there being a continuous C 1 input at 24 from a flip-flop valve 22 having its input C 2 connected to air line 20a. A continuous input C 1 is now applied to 9NOR gate by the output O 2 of 8NOR gate which together with 6 and 7 NOR gates from a latch-in AND gate 50. In order to provide 02/8NOR there must be a continuous input at both 6 NOR and 7 NOR. Continuous input C2/7NOR is provided by the feedback loop 46b from 02/8NOR passing through an emergency stop valve 64 and the required continuous input at C3/6NOR is provided by a seal-in AND gate 48 made up of NOR gates 3, 4 and 5 (52, 54, 56). In operation C1/4NOR receives 1 AND/01 output (start signal) thus producing an 01 output at 4NOR and no input at C 2 /5NOR. Also there is established by means of jet sensor limit switches 32, 34 and NOR gates 38, 43 an input at either C 1 or C 2 of 3NOR thereby providing an 01/3NOR output and no input C1/5NOR. With no input at either C 1 or C 2 of 5NOR an output is maintained in a line 58 leading to C3/6NOR and connected by a line 58b passing through a top-stop valve 65, 66 to C2/4NOR thereby connecting the output thereof to 01 i.e. atmosphere. Limit switch 34 provides a signal at inlet C 1 of 1NOR except for a short time at 180 degrees crank-shaft position when a cam 41 on the crank-shaft obstructs a gap 1, 2 in the switch circuit. Limit switch 32 provides a signal to C 1 of 2NOR except when gap 1, 2 of switch 32 is obstructed by a cam 40 at between 90 degrees and 270 degrees. To stop the press at the top of its stroke button 66 is pressed to terminate the C 2 input to 4NOR. This shifts the output at 5NOR from 02 to 01 thereby terminating the C 3 input to 6NOR. The C 2 input at 6NOR is maintained since in the absence of a C 2 input at a flip-flop 62 the output of the latter remains at 01, but at the 180 degrees crank-shaft position there is a C 2 input at 62 shifting the output thereof to 02 where it remains and terminates C 2 input to 6NOR, and when the crank-shaft reaches the 270 6 position the input C 1 to 6NOR is cut off and the press is stopped at the top of its stroke.

Delay line control gated micrologic clock generator

Abstract: A delay line and logic control gated micrologic circuit clock signal pulse train generator with each pulse waveform clock signal in synchronism with its initiating gate trigger signal. A NAND gate receives an activating gate trigger signal and immediately a voltage shift in NAND gate output with this is then passed through a delay line coil both to output path means and also back as an additional input inhibit for the NAND gate at a predetermined delay determined by the delay line. The immediately resulting voltage shift at the NAND gate output is again passed through the delay line coil with the same delay to then remove the inhibit signal from the NAND gate with again an immediate shift in the NAND gate output voltage, and with the pulse generating cycle continually repeating itself with precise pulse width and spacing between pulses in a pulse train in synchronism although delayed from the start of the activating gate trigger signal with the pulse train cycle generating action continued just so long as the activating gate trigger signal is applied.

Improvements relating to toll systems for road vehicles

Abstract: 1,219,123. Toll system for road vehicles FERRANTI Ltd. 15 Jan., 1969 [17 Jan. 1968], No. 2452/68. Headings G4T and G4Q' A toll system for road vehicles comprises a toll point for each vehicle lane, there being a sensor 11 in the road which, on passage of a vehicle causes an interrogator station to emit a signal, which signal is received by transponder (Fig. 2) on the vehicle, debits a prepaid credit unit, and sends a reply signal to the interrogator. If the vehicle has no credit or no transponder, no reply signal is sent and a cine camera 27 is actuated which records the rear number-plate. The sensor utilizes pressure, photo-electric or magneto-electric sensing and the signal may be radio, infra-red or photoelectrical. The passage of the front wheels of a vehicle over pad 11 emits a pulse which causes gate generator 12 to generate a gating pulse, e.g. of 25 ms., and which also activates transmitter 13 to emit a signal at frequency f1 through antenna 15 and also activates receiver 16. If the vehicle has a transponder, the signal is received by receiver 42 and passed through modulator 44 and AND gate 45. The other input of the AND gate is connected to a credit store (pulse counter) 51 which only emits a signal if the store has credit. It is intended that this credit store be officially credited at some chosen time interval and is secured in the transponder by lockable leads. If the vehicle has credit, one or more units are debited from the store and transmitter 46 sends the reply signal at frequency f2 which is received by receiver 16. The interrogator includes a logic network 21 including a 2-stage binary counter 22, an inhibit gate 23 and AND gates 25, 26, gate 26 being opened when the counter holds number 3 (i.e. 2 0 +2 1 =3). Counter 22 normally holds 1, the gating pulse from 12 sets it to 2, but a signal received from receiver 16 resets the counter and returns it to zero. The rear wheels of the vehicle (which have no transponder) set the counter back to 1. If, however, the vehicle emits no reply signal (i.e. no credit or transponder) the rear axle wheels set the counter to 3, gate 25 opens and camera 27 is fired for a few seconds to record the numberplate. Gate 26 opening, inhibits gate 23 and thus keeps the counter at 3 until receiver 16 again receives a signal. Thus the next vehicle which appears will activate the camera regardless of whether it is in credit or not. This waste of film may be prevented by a modification (Fig. 5, not shown) which resets the counter after each camera operation by means of a differentiator and a buffer stage. In an alternative embodiment the signals f1 and f2 are the same frequency in which case a delay circuit is provided for the receiver 16. A higher rate may be set for peak periods by installng a second interrogator station which only operates during these periods. In an alternative credit store, the credit may be added instead of subtracted.

Generator speed matcher using direct sampling

Abstract: SQUARED BUS AND SQUARED GENERATOR VOLTAGES ARE APPLIED TO TWO AND GATES RESPECTIVELY, BUS AND GENERATOR SAMPLING PULSES ARE PRODUCED WHENEVER THE SQUARE WAVES UNDERGO A POSITIVE TO ZERO TRANSITION, THE BUS SAMPLING PULSED BEING APPLIED TO THE AND GATE WHICH HAS THE GENERATOR SQUARE WAVE APPLIED THERETO AND THE GENERATOR SAMPLING PULSES BEING APPLIED TO THE AND GATE WHICH HAS THE BUS SQUARE WAVE APPLIED THERETO, SO THAT THE BUS SAMPLES THE GENERATOR AND THE GENERATOR SAMPLES THE BUS OR ENERGIZED LINE. WHEN THE GENERATOR VOLTAGE IS LAGGING THE BUS VOLTAGE, THE OUTPUT OF ONE AND GATE IS A SERIES OF POSITIVE PULSES WHILE THE OUTPUT OF THE OTHER AND GATE REMAINS AR GROUND LEVEL. IF THE GENERATOR VOLTAGE IS LEADING THE BUS VOLTAGE, THE OUTPUT OF THE OTHER AND GATE IS A SERIES OF POSITIVE PULSES WHILE THE OUTPUT OF THE FIRST NAMED AND GATE REMAINS AT GROUND. THE OUTPUTS OF THE TWO AND GATES ARE FED TO OPPOSITE INPUTS OF A BISTABLE PLISHED BY THE FIRST POSITIVE PULSES FROM THE RESPECTIVE AND GATES. A PHASE DIFFERENCE WAVE FORM IS FED TO A LEVEL DETECTOR AND A PULSE SHAPER OR GENERATOR WHICH PRODUCES A SAMPLING PULSE WHEN THE PHASE DIFFERENCE BETWEEN THE BUS AND THE GENERATOR IS 50*. THIS LAST NAMED PULSE IS USED IN TWO NOR CIRCUITS T SAMPLE BOTH OUTPUTS OF THE BISTABLE. IF THE BISTABLE IS IN THE SET STATE WHEN THIS SAMPLING PULSE OCCURS THE OUTPUT OF A FIRST NOR GATE IS A LOGICAL ONE AND A "RAISE" PULSE STRETCHER IS ACTUATED FOR PRODUCING A SIGNAL WHICH IS UTILIZED TO INCREASE SPEED. IF THE BISTABLE IS IN THE RESET STATE WHEN THE 50* SAMPLING PULSE OCCURS THE OUTPUT OF A SECOND NOR GATE IS A LOGICAL ONE, AND A "LOWER" PULSE STRETCHER WILL BE ACTUATED, AND A SIGNAL PRODUCED TO REDUCE THE SPEED OF THE GENERATOR. IF THE BUS AND GENERATOR ARE TOO CLOSELY MATCHED AND THE TIME INTERVAL BETWEEN TWO SUCCESSIVE 50* PHASE DIFFERENCE POINTS IS TOO LONG THE "RAISE" PULSE PRODUCER IS ACTUATED. IN ANOTHER EMBODIMENT, SQUARED WAVEFORM REPRESENTING WAVEFORMS PLUS A THIRD SQUARE WAVEFORM REPRESENTING THE BUS AFTER PHASE SHIFTING ARE OBTAINED, AND APPLIED TO FOUR AND CIRCUITS WHICH TOGETHER WITH A BISTABLE CIRCUIT AND PULSE STRETCHERS PROVIDE "RAISE" AND "LOWER" PULSES OR CHAINS OF PULSES DEPENDING ON THE RALTIONSHIPS OF THE GENERATOR AND BUS FREQUENCIES AND PHASE.

DTPL all-magnetic logic networks

Abstract: The design and principles of operation of two-layer domain tip propagation logic (DTPL) set-reset and complementing flip-flops are described. These magnetic thin film devices demonstrate how the inherent delay in the propagation of channeled domain tips together with the basic DTPL logic elements (inhibit gates, fan-outs, crossovers, film-film transfers, and magnetic diodes) permit logic operations to be performed in a unique manner. Peculiar to the flip-flop devices is the fact that specific channels are continuously switched and reset by a fixed pulse sequence, although the overall network may be considered as existing in a given stable state. A ripple-carry binary counter constructed by interconnecting several similar complementing flip-flop (binary counter) stages and DTPL AND gates in a single two-layer structure is discussed.

Logarithmic adaptation method and means for regulating closed-loop systems

Abstract: 1,191,785. Logarithmic and exponential computation for control systems; selective signalling. SIEMENS A.G. 8 May, 1968 [19 June, 1967], No. 21895/68. Headings G4G and G4H. [Also in Division G3] In a control system the effect of a perturbing element such that x = Vy where x = output, y = input, and V is an unknown variable factor is overcome by introducing into the input of the element an exponential device and into its output a logarithmic device, so that x 1 =y log b a + log b V where a, b are bases, x 1 = output of the logarithmic device (Fig. 2, not shown), so that the perturbation becomes an additive logarithmic factor which may be compensated. The control signal may be logarithmically modulated, compared with the logarithm of the controlled variable, and the resultant logarithm of the quotient may be utilized to control the system in exponential dependence on its output. Diode resistor circuits or digital circuits may be utilized to introduce the logarithmic and exponential functions. A control system 4 (Fig. 3) comprises an integrated perturbing element 1 of variable gain V 2 and a proportionate element of gain V 1 . The input is preceded by an exponential device 2 of output a y , and amplifier 7 of output y, and a differencing circuit of output #, while the output x is followed by a logarithmic device 3, whose output x 1 is fed back to the differencing circuit for comparison with a control signal log b x w derived from control signal x w over logarithmic device 6. It is shown that x 1 = log b x = y (log a/log b) + log V 1 V 2 . In a further control system (Fig. 4) a dividing device 10 receives control signal x w and output signal x fed back from the control system 4, and its output is switchable to logarithmic device 11 producing a signal log (x w /x) = #, which is amplified at 7 and applied to the control system through exponential device 2. Alternatively 11 is switchably replaceable by a three-state trigger the relation between whose output A and input E are as shown, with reciprocal input values E 1 , E 2 lying on and at either side of the intersection of a fictitious logarithmic characteristic L with the abscissa, so that a logarithmic characteristic is reproduced at three points. Logarithmic and exponential functions may be introduced digitally (Fig. 5); an input signal E being applied through a differencing circuit to a symmetrical 3 stage trigger 16 producing a pulse at + output for positive input and a pulse at - input for negative input, to energize AND circuits 17, 18 together with the output of constant frequency pulse generator 19; such pulses being selectively transmitted to forward or backward inputs y, r of binary counter 20 having six stages weighted from 2- 2 to 2 3 , operating a digital/analogue converter 21 directly and a digital/analogue converter 22 through selector 23, whereby gate circuits step differing values of input impedance of D.C. feedback amplifiers 24, 25. In amplifier 24 the input impedances are stepped inversely to the weightings, and it is shown that the content of counter 20 is reproduced linearly, and with switch 60 closed the output A 1 is fed back to differencing circuit 15, so that counter 20 varies until input E and output A 1 are in agreement. In amplifier 25, the counter 20 outputs are connected to respective OR circuits 26 to 30 together with an input from the next subsequent OR circuit, and produce output pulse when one or more input pulse is received, so that a signal at any one counter output produces signal at the outputs of all OR circuits associated with coun - ter circuits of lesser significance. Adjacent OR circuits are connected in pairs to exclusive OR logic circuits 31 to 35 producing outputs only when differing logic signals appear at the inputs. Gate circuits 36 to 40 are thus operated to connect respective input resistors to the amplifier 35 stepped logarithmically and inversely to the powers of the places of counter 20. For realization of the logarithm of zero, a NOT circuit 41 is connected to output of OR circuit 26 to operate switch 42 inserting a resistance R -00 of value such that output A2 of amplifier 25 is at its limit, while for realization of log 2‹ = 1 the exclusive OR gate unconnected to the amplifier produces a signal, and may be omitted. Further AND gates 43 and OR gates 44 may be introduced to increase the number of steps, and A2 = U log b (E/kU) with switch 60 horizontal. With switch 60 vertical, it is shown that for feedback of A 2 to 16, A 1 = Ub (E/U) so that logarithmic or exponential functions may be thereby selected. A modification utilizing a shift register controlling similar exponential or logarithmic digital to analogue converters is described (Fig. 6, not shown) and a further modification of Fig. 4 (Fig. 7, not shown) employs stepping AND gates operating a shift register 45 controlling exponential or logarithmic input amplifier resistances. A three state amplifier utilizing positive feedback amplifiers and potentiometrically set operating levels is described (Fig. 8, not shown).

Single element plural lane detector

Abstract: 1,174,748. Road traffic detectors. TATEISI ELECTRONICS CO. 24 July, 1968 [17 Aug., 1967], No. 35354/68. Heading G4Q. In apparatus for detecting vehicles having a detector element 1 dimensioned to extend across a plurality of lanes, the output from the detector is changed by the presence of a first vehicle in the field of the detector and is compared with a first reference value to give an output S1 indicating the presence of the first vehicle, the output is also memorized in a circuit 12 and a signal corresponding to the difference between the memorized value and the output from the detector is also determined and this is compared with a second reference value to produce a second output S2 upon the detection of at least one more vehicle in addition to the first vehicle. As shown, when a vehicle M1 is in the field of the loop 1, the frequency of oscillator 2 is reduced. The output (A, Fig. 2, not shown), from mixer 4 obtained by comparing the output of oscillator 2 with a reference oscillator 3, increases and is fed to trigger a monostable circuit 5. The output (B) from the monostable circuit 5 is integrated at 6 and passed via an amplifier 7 to a Schmitt circuit 8 so that when the amplifier output (D) reaches a certain value (V1) the circuit 8 switches to indicate at S1 the detection of the vehicle M1 The output (C) of the integrating circuit is periodically reset. The change in output of the Schmitt circuit 8 resets flip-flop 10 so as to enable AND gate 11 to pass the output S1 so as to charge a capacitor C2 (I), and turn ON field effect transistor Tr2. Each output pulse from the monostable circuit 5 turns on transistor Tr1 so that output pulses (J), corresponding to the difference between the output of 5 and charge on capacitor C2, of decreasing amplitude are fed via C1 to an integrating circuit 13. The output (K) of the integrating circuit 13 is amplified at 14, and when the output (L) of amplifier 14 is less than a predetermined value (V2) the output of a Schmitt circuit 15 is such as to reset the flipflop 10 and prevent any further charge occurring on C2. If the vehicle now passes out of field of the loop 1 the output of the Schmitt circuit 8 changes to zero and discharges C2 to reset the arrangement. However, if the first vehicle M1 is still in the field of the loop and a further vehicle M2 occurs in the next lane to also effect the field of the loop 1, the output from the oscillator is further reduced, this increases the output frequency (A, Fig. 3, not shown), from mixer 4 and that (B) of the monostable circuit 5. The output from the circuit 5 is compared with the stored voltage on the capacitor C2 in circuit 12 and the output (C) from the integrating circuit now increases in value. When a certain value (V3) output from the amplifier 14 is reached, the output of Schmitt circuit 16 is changed. As Schmitt circuit 15 no longer holds the flip-flop 10 reset it becomes set by the output from 8 and gate 17 is enabled to give an output S2 indicating the presence of another vehicle M2 as well as M1. The detection of vehicles in three or more lanes may be achieved by connecting a corresponding number of further comparing circuits 16 and gates 17. Traffic control of cross-roads (Fig. 4).-A detector loop 1 may be arranged across a lane for left turning vehicles and a lane for straight ahead and/or right turning vehicles. Control of the traffic signals for these lanes is then obtained from the detector. Assuming a vehicle M4 is waiting to turn left this gives an S1 output from the detector arrangement. Vehicles passing over the detector to go straight ahead or right give outputs S2. When no output S2 occurs the traffic control signals can be changed to allow vehicles to turn left.

Anti-jamming circuit for multi-frequency signal detector

Abstract: A jam-proof circuit for use with a multi-frequency signal detector system to prevent noise from erroneously actuating the detector system. The circuit employs substantially similar high and low-band exclusive OR circuits interposed between the output of the multi-frequency signal detector means and associated logic circuitry. The exclusive OR circuitry prevents noise from causing erroneous indications to be produced by the logic circuitry which comprises an individual AND gate corresponding to each digit that may be signalled. The digits are identified by the simultaneous transmission of a plurality of different frequencies.

Recording and playback system incorporating a first character positioning system

Abstract: 1,210,586. Magnetic card apparatus. INTERNATIONAL BUSINESS MACHINES CORP. 3 Jan., 1969 [15 Jan., 1968], No. 57758/68. Heading G4M. The apparatus is similar to that disclosed in Specification 1,210,587 but is mainly concerned with the recording and playback of a reference character at the beginning of each track. Initially the card is driven at high speed in the reverse direction (23) until photo-cell 19 is covered, track return latch 67 is set followed by D1 which resets 67 and initiates forward drive (24). If a reference character has been previously recorded on the track selected, it is gated at 75 with D1 and 19 outputs and counter 77 gives an output when all bits of the reference character have been read, to reset D1 and set D2 or D6 depending on whether record or playback mode has been selected. In the record mode the card is driven in reverse and the reference character bits are applied to time out circuit 87 which causes an output from 89 when the reference character is correctly positioned between the read and write heads, D2 being reset and D3 set. If the reference character was found to be in error or missing completely, D4 may be set to initiate recording of a reference character, the card being driven in reverse at high speed until photo-cell 19 and gate 107 reset D4 and set D5, the latter initiating forward movement of the card and gating the reference character from a register 108. Bit counter 77 indicates when all the bits have been recorded to reset D5 and set D3 via gate 115. With a correctly recorded reference character, operation to record data characters is as described in Specification 1,210,587. If the playback mode has been selected, operation is as described above for the D1 cycle and D6 is reset when a data character has been read. If a change to record mode is required before the data characters are read, D2 is set by gate 117 to reposition the reference character between the read and record heads. Similarly if a change from record to playback mode is required before the first data character is recorded, gate 119 sets D1 and resets D3, D1 being reset and D6 set when the reference character has passed the read head. If a reference character is not sensed during the playback mode, the operator can proceed to read subsequent data characters or can choose to record a reference character by changing to the record mode (gate 103 sets 67 followed by D1

Improvements in or relating to high voltage circuit protection arrangements

Abstract: 1,100,647. Protective arrangements. MARCONI CO. Ltd. 29 Dec., 1965 [23 April, 1965], No. 17312/65. Heading H2K. [Also in Division G1] The fact that overload conditions are occurring in a high voltage line, is transmitted over a radiation link to alarm or safety apparatus, the radiation transmitter being fed by a pulse generator having an operating characteristic dependent on the line condition. In the line to be protected there is inserted a series resistance, the voltage drop across which controls the mark-space ratio of a blocking oscillator T. The oscillator output may be amplified and is applied to an infra-red source, e.g. a GaAs diode, the pulsed output from which is received at a low voltage station by a photo diode detector 10. The detector output is amplified and applied to a Schmidt trigger circuit 12 which passes only pulses above a predetermined amplitude, shaping those that are passed. Connected to the trigger circuit output is a timing circuit 13 (a one-shot multivibrator) and an AND gate 14. The timing circuit is triggered by the trailing edges of pulses from the Schmidt trigger. Under normal line conditions the transmitted pulses representing this condition are sufficiently spaced apart that a timing circuit pulse ends before the next pulse from trigger 12 (Fig. 2, not shown). However, if a voltage overload occurs, the mark-space ratio of the pulse generator rises substantially and a pulse from the Schmidt trigger coincides with a timing circuit pulse, producing an output from the AND gate to actuate the alarm. The device is also provided with a fail safe circuit connected to another output of the Schmidt trigger and providing one input to an OR gate 15, the other input of which is from the AND gate 14. An output from either the AND gate or the fail safe circuit is passed on to a resettable bistable circuit 17 which operates the alarm and/or safety means when over-load occurs. The fail safe circuit comprises a detector 16 and inverting amplifier 20 and gives an output when no pulses are obtained from the detector 10.

Improvements in or relating to machine recognition of speech

Abstract: 1,101,721. Automatic speech recognition. NATIONAL RESEARCH DEVELOPMENT CORPORATION. 1 Feb., 1965 [31 Jan., 1964], No. 4266/64. Heading G4R. Speech recognition apparatus comprises a delay network to which the speech signals are applied, a number of correlators coupled to the delay network for correlating the speech waveform with delayed output signals from successive points on the network, means for decoding the outputs from each of the correlators and a decision network coupled to the decoding means for indicating the characteristics of the input speech signals. The purpose of the correlating step is to distinguish between different frequencies regardless of their relative amplitudes. For any given value of delay between two sampling instants one frequency gives a positive correlation and another gives a negative correlation. If tappings are taken at three adjacent points A, B; C on a delay line carrying a speech wave, the magnitudes of the signals can have four possible relationships: A B B>C. If these relationships are determined, the nature of the waveform can be found and the vowel which it represents. In Fig: 2, the speech signal from a source 10 is applied to a filter 12 having a non-linear response designed to improve the clarity of the signal. The output is passed via an automatic gain control 14 which restricts peak amplitudes to a certain maximum value but allows the other parts of a word signal to vary in amplitude. Frequency discriminator 16 divides the input wave into a high frequency part on line 17 and a low frequency part on line 18. Both parts are applied to delay lines 19, 20. Associated with each delay line are two correlation circuits 21, 22 and 23, 24. Each receives the undelayed speech signal and two delayed versions from different points on the delay line. Each correlation circuit comprises a transistor circuit in which signals A and B are compared and signals B and C are compared and the results combined. An output integrator receives positive current if the value of B is between the values of A and C and negative current if B is greater or less than both A and C. The four output signals are recoded in a diode circuit 25 to produce a sequence of markings on one of sixteen leads. A recognition circuit 26 consists of a number of sequentially operable trigger and gate circuits designed to respond to particular conditions appearing successively.

Improvements in or relating to electrical control systems

Abstract: 1,127,181. Electric selective signalling. UNITED KINGDOM ATOMIC ENERGY AUTHORITY. 25 Jan., 1966 [26 Jan., 1965], No. 3411/65. Heading G4H. [Also in Division H3] A logic circuit provides output pulses characteristic of the number of inputs present, and for the three-input basic circuits described provides a uniform series of output pulses if all inputs are present, a reduction of pulses to one third if one input is removed and no output for either one or zero input. Magnetic storage cores F 1 -F 3 are used in the basic logic circuit shown in Fig. 3, in which two storage cores are energized in opposite respects if an input A-C is present simultaneously with a respective three phase clock pulse # 1 -# 3 . If two inputs are present such as A, B, core F 1 only is switched and reset during clock pulse periods #2, #1, respectively, the other two cores being quiescent. An output pulse is then obtained during clock pulse period # 1 alone which passes through a resetting winding r. If all inputs are present then all three cores are switched and reset in turn and produce output pulses in all of the clock pulse periods # 1 , # 2 and # 3 . No output is obtained for either a single or zero input. A frequency sensitive detector connected to the output determines the number of inputs present. As shown in the lower part of the Figure the outputs of several basic devices may be combined using magnetic storage cores, these cores being connected in cascade with the first core energized for resetting by pulses #INT of three times the three-phase frequency. A combined output is obtained if each basic circuit has two or three inputs present, the frequency of the output being reduced if any one basic circuit has less than three inputs. An alternative basic circuit comprises a laddie, Fig. 5 (not shown), having hold windings (a), (b), (c) arranged in pairs on alternate rungs, each of three inputs (AA 1 )-(CC 1 ) being connected to two hold windings each on a different rung. Two laddies may operate in cascade, the output winding of one being connected to the reset winding of the other. A further arrangement of laddies, Fig. 6 (not shown) is similar to Fig. 3, the combined output circuit serving as a trip line for a transducer. A number of trip lines T 1 ,T 2 ,T 3 may be combined as shown in Fig. 7, to control a transducer Z, the final coded output of any trip line being detected by frequency meters PM1-FM3 The pulsed output is converted to a D.C. signal in converter C1-C3, and is recoded to provide an output despite minority failure of the trip lines by gates 29 each energized by a different two of three phases # 1 -# 3 . These are applied to an AND gate 40 from which the loss of any one input is recognized by a 3 : 1 frequency change at meter FM4. Each of the three phases is taken from different generators 41 to prevent the network output from disappearing if one generator fails. In this arrangement the failure of a minority of inputs on any line is detectable by the pulse pattern appearing at meters FM1-FM3, while any minority of trip line failures is detected by meter FM4. Proof testing without operating the transducer may be carried out in any of the three circuits by interrupting the trip line at X. The arrangements disclosed are applicable to plant or process control.

Improvements in or relating to synchronising code patten detectors

Abstract: 1,127,101 Electric selective signalling MARCONI CO Ltd 20 March, 1967 [16 June, 1966], No 26832/66 Heading G4H Also in Division H4] An arrangement for detecting a code pattern of a predetermined sequence of bits, eg a synchronizing signal in a pcm system, comprises a shift register having a number of stages which is less then the number of bits in a sequence, means for feeding the sequence to the register, means for shifting the register in steps, in each of which the register registers a different sub-sequence of bits, means for detecting the sub-sequences registered in the successive steps, a counter for counting the steps taken and for providing a pattern recognition signal when a count sufficient to permit registration of the whole pattern has been made, and means for resetting the counter if, at any step in the count, an incorrect sub-sequence combination is registered As shown in Fig 1, the synchronizing code, consisting of the sequence 1101010101010101, is fed to a three stage shift register 1 which is shifted step by step by pulses from a unit 2 which are also supplied to an AND gate 3 Three code detectors 5, 6, 7 are connected to the shift register so that they respond to the sub-sequences 110, 101 and 010 respectively In operation, when the first combination is registered (110) the output of detector 5 switches a bi-stable device 9 which opens AND gate 3 The next pulse from unit 2 steps a 13-step counter via gate 3 and shifts register 1 by one step so that it registers 101 This combination is recognized by detector 6 thus inhibiting gate 8 from providing an output and enabling gate 3 to remain open Counter 4 is stepped by the next pulse from 2 and the register shifted to register 010, this sequence being recognized by detector 7 so that gate 8 remains inhibited and gate 3 remains open Detectors 6 and 7 continue to inhibit the gate 8 until the end of the synchronizing signal is reached, a full count is reached at 4 and an output signal is obtained indicating that the correct sync signal has been received Should an error occur in the sync signal, detector 6 or 7 will fail to inhibit the gate 8, bi-stable 9 will be switched over to close gate 3, and the counter 4 will be reset to zero The detector then awaits the registration of the 110 sequence to restart the count In a modification, Fig 2 (not shown), using the same synchronizing code, a two-stage register co-operates with a pair of detectors responding to 11 and 00 respectively When the initial sequence 11 is detected a bi-stable device is switched to enable an AND gate controlling the counter which continues to count if the correct sync signal is being received Should the combination 11 or 00 be detected after the initial sequence a signal is provided via an OR gate to reset the counter

A circuit for a sorting unit of a programmed automatic measuring device especially adapted for testing of integrated control circuits

Abstract: A circuit for a programmed automatic measuring device, especially for integrated circuit testers comprising a plurality of input logics for determining the conformity of measured test results with predetermined standards, with two parallel AND gates, one with input negation, and an OR gate with output negation arranged in series with the AND gates; flip-flops in series with the input logics; and means for automatically conforming the test result to the respective standard if the respective test results is not to be evaluated.