scispace - formally typeset
Search or ask a question

Showing papers on "AND gate published in 1970"


Patent
Tritus F Watson1
06 Apr 1970
TL;DR: In this paper, the stator windings of a brushless DC motor are energized through individual silicon controlled rectifiers arranged in a ring counter circuit which is triggered from a pulse source.
Abstract: The stator windings of a brushless DC motor are energized through individual silicon controlled rectifiers arranged in a ring counter circuit which is triggered from a pulse source. When the motor is to be started, an AND gate forces the first pulse to trigger a specific silicon controlled rectifier. The AND gate then permits subsequent pulses to be steered to various silicon controlled rectifiers in the desired sequence. The pulse source is synchronized through an OR gate coupled to receive signals from each stator winding. When a given silicon controlled rectifier is turned off, the corresponding stator winding is deenergized. The motion of the rotor, however, induces a counter EMF in the deenergized winding. This counter EMF is applied through the OR gate to synchronize the pulse source.

42 citations


Journal ArticleDOI
TL;DR: Two examples serve to illustrate the criteria used in the design of domain-tip propagation memory devices as well as to demonstrate the use of the bidirectional shifting and magnetic logic capability of the technique.
Abstract: Magnetic domain-wall motion memory devices have been under development for a number of years. Several techniques have been devised for controllably introducing a pattern of magnetic domains into a saturated background material and for shifting these domains between input and output locations. A particularly flexible version of this class of device, lending itself as well to the performance of magnetic logic, is channeled domain tip propagation. The technique is reviewed. Channeled domain-tip propagation requires some means of defining a pattern of narrow low coercive-force paths within a background material of high coercivity. Several techniques are described which include the use of the surface roughness of an underlying metallic film and the direct coupling between hard and soft magnetic layers for locally modifying coercive force in an appropriate pattern. The variety of magnetic channel structures which can be produced are described along with the resulting magnetic properties and their application to memory and logic devices. Their properties are functions of the size and shape of the channel structures and depend on their orientation with respect to the easy axis of the film and on the composition of the latter. Theory and experiment are presented which describe the dependence of channeled domain-tip coercive force and velocity of propagation on the variables mentioned above. The operation of various magnetic logic elements, including AND, OR, and NOR gates and nonreciprocal propagation paths, i.e., diodes, is discussed. The use of inductive and magnetoresistive schemes for detecting output signals is described. Several specific examples of the application of domain-tip propagation techniques to different memory and logic devices are given. The design and operation of counters, long shift registers, a last-in first-out (LIFQ) list memory, and a first-in first-out (FIFO) serial data buffer memory are discussed. These examples serve to illustrate the criteria used in the design of domain-tip propagation memory devices as well as to demonstrate the use of the bidirectional shifting and magnetic logic capability of the technique.

22 citations


Patent
21 May 1970
TL;DR: In this paper, a plurality of normally off, pushbutton secure switches are located at an outer side and a same plurality of presettable, multiple positionable, secure switches were located at the inner side of a door guarded by a latch, with the first nonsecure switch being electronically connected through a set-reset flip-flop to the first position of all of the secure switches, the second non-secure switch through a reset resetting to the second position, and so forth.
Abstract: A plurality of normally off, pushbutton secure switches are located at an outer side and a same plurality of presettable, multiple positionable, secure switches are located at an inner side of a door guarded by a latch, with the first nonsecure switch being electronically connected through a set-reset flip-flop to the first position of all of the secure switches, the second nonsecure switch through a set-reset flip-flop to the second position of all of the secure switches and so forth. The output of each of the secure switches is connected to the input of an AND gate and the output of all of the AND gates are connected to the inputs of an OR gate, with the output of the OR gate and the other inputs of all of the AND gates being connected to an electronic counter formed by a plurality of toggle or clocked flip-flops. The output of the counter is connected through an AND gate of an electric solenoid circuit which is normally blocked from actuating the solenoid by a transistor, the transistor when driven to a conducting state permitting actuation of the solenoid. A timer circuit, including inverters, transistors, and AND gate, and other electronic components, is connected to the inputs of all of the secure switches through an OR gate and is also connected to the counter beginning an electronic timing upon predetermined correct momentary operation of one of the nonsecure switches to limit the total amount of time that the nonsecure switches can be correctly operated in proper sequence to finally permit energization of the electric solenoid. Thus, with the electrical circuitry including the electronic components, the secure switches may be set to any combination of multiple settings which determines the required sequence of operations of one or more of the nonsecure switches, the secure switches in their connection in the circuit requiring transmission therethrough in order or sequence. In the sequence of operation of the nonsecure switches does not follow the order of secure switches, the entire circuitry is reset to starting position including the timer circuit and if the time period of the timer circuit expires the entire circuitry is reset, thereby requiring exact operation of the nonsecure switches within a determined time period in order to energize the solenoid. The solenoid is mounted blocking operation of the latch guarding the door so that when the solenoid is energized, the latch can be operated and the door opened.

17 citations


Patent
09 Sep 1970
TL;DR: In this article, a traffic monitoring system has been proposed for directing a plurality of beams of electromagnetic radiation across a carriageway in such a way that the manner of interruption of the beam system by a vehicle depends on the particular lane occupied by the vehicle.
Abstract: 1,204,484. Detecting traffic flow. GENERAL ELECTRIC and ENGLISH ELECTRIC COMPANIES Ltd. 30 Nov., 1967 [30 Nov., 1966], No. 53595/66. Heading G4Q. A traffic monitoring system has means for directing a plurality of beams of electromagnetic radiation across a carriageway in such a way that the manner of interruption of the beam system by a vehicle depends on the particular lane occupied by the vehicle. Signals so obtained may be used to indicate occupancy or to control the traffic. In Fig. 1 beams of modulated infra-red energy are directed by sources 1, 2 towards sensors 4, 5 which feed receivers 6, 7 and Schmitt triggers 7, 8. The outputs of the latter are normally of such polarity that an AND gate 13 is disabled. A vehicle travelling in the fast lane interrupts the beam from source 1 and changes over the Schmitt trigger 8 to enable the AND gate. A short time later the vehicle interrupts the beam from source 2 and changes over the Schmitt trigger 9, this output being differentiated and applied to the AND gate which now triggers a monostable circuit 14 and lights a lamp 15 for a short time. A vehicle in the slow lane interrupts beam 2 first, and the differentiated output of Schmitt trigger 9 will have ceased before an output is obtained from 8, so that no indication is given. The differentiating circuit 12 may be in the other or both outputs if it is desired to indicate vehicles in the slow lane or both lanes. In the latter case, a second AND gate, monostable circuit and lamp are used. The lamp may be replaced by a counter or other monitor, or control circuit. Application to more than two lanes.-In this case the beams diverge towards the fastest lane, the transverse position of the vehicle depending on the time elapsing between interruption of the two beams. To compensate for varying vehicle speeds a third beam is provided, parallel to one of the other beams, and the time between interruptions of the parallel beams is a measure of the vehicle speed. The output signal of the system can then represent the ratio between the times between two pairs of beams. If the two parallel beams are perpendicular to the carriageway errors due to varying widths of vehicles are avoided. In an elaboration of this system (Fig. 2) four beams are used as shown, the outputs from the sensors S1-SA being applied to logic circuitry 20 comprising four monostable circuits connected in cascade by means of three AND gates. Only when the input signals are applied in a particular time sequence will all the monostable circuits and AND gates be operated, and this sequence is unique for a particular lane. By repeating such circuitry for each lane a lane indication can be given. The parallel beams S2, S3 also give a speed indication by means of a pair of start/stop gates 21. The first gate initiates a ramp generator which is stopped by the second gate, giving a voltage inversely proportional to vehicle speed. This voltage is converted to frequency in a unit 22 which is controlled by the second gate, and a counter 23 is calibrated to show the particular lane occupied. For discrimination only over half the carriageway the fourth beam may be omitted. Modifications using reflectors.-In the system of Fig. 1 the sources and sensors may be on the same side of the carriageway, with a reflector on the other side. For more than two lanes, reflectors are placed one beside each lane so that the number of beams interrupted indicates the particular lane occupied. Alternatively, the output of the sensor for the last lane is fed via an AND gate to which is fed the signals from the other sensors through a NOR gate. The reflectors are embedded in the road surface with an access channel for the incident radiation. For three lanes, the sources and sensors can be arranged so that the centre lane intercepts two beams while the two outside lanes intercept one beam each. Alternatively the beams are staggered along the carriageway, the first beam traversing one lane, the second two lanes &c., so that the first beam interrupted indicates the lane. In another version the beams are inclined at an angle to the horizontal so that vehicles in only one or some of the lanes can intercept the beam. This modification is useful in tunnels or under bridges. Sources and sensors.-The sources may be sub-lasing gallium arsenide diodes modulated by a transistor blocking oscillator and emitting a beam-width of one degree. The sensors are photo-diodes with transistor amplifiers. Both are as in Specification 1,115,802.

10 citations


Patent
02 Mar 1970
TL;DR: A system for determining the average length of intervals between pulses in a finite train, including a pulse counter, two alternately operating interval timing devices, an arithmetic divider, and storage and logic circuits, is described in this article.
Abstract: A system for determining the average length of intervals between pulses in a finite train, including a pulse counter, two alternately operating interval timing devices, an arithmetic divider, and storage and logic circuits An interval-adaptive track gate arrangement provides discrimination against spurious pulse intervals

9 citations


Patent
Gerald Kevin Mcauliffe1
18 Jun 1970
TL;DR: In this article, a timing recovery circuit based on the departure from the zero crossing of an analog signal is disclosed, in which the amplitude and polarity of the resulting signal are stored in a hold circuit which applies the signal to a means for determining the direction of a possible transition.
Abstract: A timing recovery circuit based on the departure from the zero crossing of an analog signal is disclosed. The departure from the zero crossing is proportional to the amplitude of a sample taken at a time when an analog signal is expected to experience a zero crossing. The amplitude and polarity of the resulting signal are stored in a hold circuit which applies the signal to a means for determining the direction of a possible transition. In the meantime, the input signal is applied to a data decision circuit which may be a clocked flip-flop, for example, which samples the polarity of the analog signal half a bit time later than the first sampling of the analog signal. The resulting output (a ''''1'''' or a ''''0'''') is simultaneously applied to the means for determining the direction of a possible transition and to a means for determining if a transition has in fact occurred. The former is an inverting gate which, in response to the polarity of the output of the clocked flip-flop, provides at its output either the output of the sample and hold circuit or an inverted version thereof. The latter means consists of a delay device such as a one bit shift register to provide an output delayed by one bit and an exclusive OR gate, the terminals of which are connected to the input and output of the delay device. The OR gate provides an output only when the polarities of the samples at the input and output of the delay device are different. This circuit, in effect, makes a comparison between the polarity of a present bit and a previous bit to determine whether or not a transition has occurred. The output of the exclusive OR circuit and the inverting gate are applied to another gate. This gate is operative only if the exclusive OR provides an output indicating that a transition has occurred and the output of the inverting gate is applied to an averaging filter which provides a control signal for adjusting the frequency of a variable frequency oscillator; the zero crossing of which is to be synchronized with the zero crossings of the analog signal.

9 citations


Patent
03 Dec 1970
TL;DR: In this paper, a safety gate is mounted at the end of a pair of parallel arms pivotally connected to the ram so that the arms and gate are conjointly movable in the vertical direction with the ram.
Abstract: A press having a ram adapted to move vertically toward a die surface, including a safety gate automatically swingable to move in front of the die facade. The gate is mounted at the end of a pair of parallel arms pivotally connected to the ram so that the arms and gate are conjointly movable in the vertical direction with the ram. The arms are simultaneously linked to the frame of the press by a crank lever system so that the downward vertical movement of the ram swings the gate in front of the die facade in advance of the closing of the ram.

7 citations


Patent
18 Mar 1970
TL;DR: In this paper, the authors present an approach to represent input information by the probability that a level in a clocked sequence of logic levels will be ON, and apply the so represented information to the computing element(s) performing digital computation, and convert the stochastically represented outputs of the computation into analogue or digital information valves.
Abstract: 1,184,652. Stochastic computation. STANDARD TELEPHONES & CABLES Ltd. 3 March, 1967 [7 March, 1966], No. 9871/66. Headings G4A, G4D and G4G. [Also in Divisions G1 and G3] General.-A computer assembly comprises one or more digital computing elements, means for representing input information stochastically by the probability that a level in a clocked sequence of logic levels will be ON, means for applying the so represented information to the computing element(s) performing digital computation, and means for converting the stochastically represented outputs of the computation into analogue or digital information valves. Theory.-Analogue variables are presented as probabilities that a specific binary or multilevel event will occur (or generally the probability that a specific configuration representing one of several possible events will occur), and a quantity or event may be scaled as a probability 1 > P > 0, and represented by a sequence of logic levels or states of the inputs and outputs of the computer elements; which representation, e.g. by the adaptive device of Specification 1,099,574, is stochastic since the event or quantity is defined by the statistical properties of a sequence as to the probability that it represents a given event or quantity. In affine symmetric binary representation, analogue quantity -E 0, the states being permanently on or off for maximum or minimum values of V and randomly fluctuating therebetween (or OPEN) for zero. Thus V = [p (ON) - p (OFF)] E 9/ for a sequence in a ternary device wherein p (on) and p (off) are the relative frequencies of on and off conditions and for 0 0 is a scaling factor; Zero being represented by "OFF" and infinity by "ON" and extensible to negative quantities by multiplication by (- 1). In symmetric projective ternary representation, when V#0 and when V 1 = E - V for affine asymmetric binary representation, V 1 = - V for affine symmetric binary and ternary, projective symmetric ternary, hyperbolic ternary, and trigonometric 1 binary V 1 = - for projective binary represen- V tation. Fig. 6 shows a multiplication circuit for afline symmetric binary representation. If + denotes OR switching and juxtaposition indicates AND switching, while a superposed bar indicates a Boolean inverse so that a = 0 if and only if a = 1 a = 1 if and only if a = 0, the levels a, b as shown are applied through inverters to AND gate 1 as #a #b and directly to AND gate 2 as a, b, so that output of OR gate 3 is #a #b + ab which represents the scaled products of the variables represented by the sequences of a and b; the multiplier being an equality gate giving ON output if and only if its inputs are identical. For multiplication of further quantities, such multipliers are cascaded. An affine ternary representation multiplier is identical logically with that of Fig. 6 and (Fig. 1, o, p, not shown). For a multiplier in projective binary representation, a cross coupled flip flop FF (Fig. 3) receiving inputs X, Y is clocked to change over to a value dependent on its prior state and preceding inputs X, Y; the output Z from an OR gate energized from two AND gates receiving X, Y and the flip flop outputs being equal to a new input X if the flip flop output Q is ON, and equal to the complemented new input #Y if the Q input is ON. The device realizes the transformation For multiplication in projective binary representation (Fig. 4) a clocked cross coupled flip flop CCFF receives inputs AB, #AB from AND gates respectively energized from inputs A, B; directly and through inverters in synchronous logic, while in asynchronous logic the clock pulses may be obtained from a local oscillator, or triggered from a change of output if the inputs are mutually exclusive. A further delay flip flop in one input acts as correlation isolator (Fig. 7, not shown). For evaluation of squares and higher powers utilizing plural multipliers, input isolators utilizing clock pulse delay flip flops (Figs. 7, 8, not shown) are inserted to avoid autocorrelation of the inputs, whenever identical signals are applied to multiple paths, in stochastic computation. Autocorrelated sequences may be de-correlated (Fig. 21) by introducing random delays whose maximum delay # autocorrelated depth from noise sources changing over triggers at random intervals to randomize the clock pulses of flip flops FF1, FF2 when the noise exceeds a predetermined level. The random states are transferred to flip flops FF3, FF4. Flip flops FF5, FF6, FF7 connected as a shift register to the direct inverted input hold previous input states at unit, two, and three delay intervals respectively, and flip flops FF3, FF4 gate one of these delayed inputs through three input AND gates and a common OR gate to the output line, so that at each clock pulse a random delayed replication of the input appears on the output. In an adder for symmetric and asymmetric binary affine representation (Fig. 9), a first flip flop FF is triggered from a noise source with grounded inputs, and its output is applied to a second flip flop FF emitting an ON level to AND gate 4 and an OFF level to AND gate 5, or vice versa with equal probability, so that the probability p (Z) of output from OR gate 6 is ¢ (PA + PB) from gates 4, 5. It is shown that the output is 1/k the sum of the inputs for a k input adder, and for 2 inputs a trigger pulse is applied to clock input of a first flip flop when signal from random noise source exceeds a preset threshold, to change its state, since its inputs are in a random condition at the instant of a clock pulse. Random sequences carrying information are generated in a comparator with binary output having a random first input and a fixed or variable second input responsive to input voltage or digital code; the random input containing all levels with equal probability. Fig. 10 shows analogue/stochastic converter generating random sequences comprising a comparator receiving an analogue input and an input from a digital to analogue converter triggered at T by a series of flip flops FF, each in turn triggered on its clock line from a random noise source exceeding a predetermined threshold. The flip flops are in random state so that the D/A converter feeds a random level to the comparator. If at a clock pulse applied to an output flip flop fed from the converter, the analogue input exceeds the random input, the output flip flop is ON and otherwise it is off, so that the output sequence is an affine binary stochastic representation of the analogue input if the D/A conversion is linear. Alternatively (Fig. 11, not shown) for digital input the latter is applied directly to a digital comparator also receiving the random digital output of a series of flip flops

6 citations


Patent
19 Oct 1970
TL;DR: In this article, a circuit for performing AND gate function using two-state D.C. switching logic as the gate inputs, including a sequence of flip-flop stages connected as a pulse frequency dividing network, is disclosed.
Abstract: There is disclosed a circuit for performing an AND gate function using two-state D.C. switching logic as the gate inputs, including a sequence of flip-flop stages connected as a pulse frequency dividing network. Each flip-flop stage of the network is individually actuated into its operative role in the divider network by application of one of the logic signal inputs thereto as the stage operating potential. Simultaneous presence of TRUE logic conditions are sensed by application of a pulsing signal of predetermined frequency to the input of the dividing network and detection of the divided frequency at its output. Failure of any component or combination of components of this circuitry produces a no-output condition which is deemed failure in a failsafe manner.

5 citations


Patent
25 Nov 1970
TL;DR: In this paper, a binary counter is used for tuning a musical instrument, where the counter is initially set to the complement plus one of the correct count for the note by means of a note selector switch and a diode matrix.
Abstract: 1,213,794 Tuning musical instruments; measuring frequencies R S PHILLIPS 5 March, 1968 [5 Dec, 1966], No 54377/66 Heading G4A and G5J In an apparatus for use in tuning a musical instrument, a pulse of duration proportional to the frequency of a note is derived from a signal A produced by a transducer 7 and applied to open a gate through which high frequency oscillations are applied from a generator 13 to a binary counter 14 The counter is initially set to the complement plus one of the correct count for the note by means of a note selector switch 5 and a diode matrix 17 (Fig 4, not hown), whereby the counter is returned to zero if the instrument is in tune Otherwise the final reading of the counter indicates the departure from correct tuning At the completion of each count the counter reading is transferred by a monostable circuit 18 to a lamp display 6 and a meter system 8, 15 In order that the counter may function in the same frequency range for all octaves, the circuit between transducer 7 and gate 12 includes a switched divider system 4, 10 whereby between one and seven binary dividers may be introduced A final divider 11 halves the frequency of the gate signal The input signal to 11 triggers a monostable circuit 16 so as to operate 5 and 17 to set in the initial count before each count, whilst the output signal from 11 resets circuit 16 and triggers circuit 18 The lamp display comprises five lamps of which the centre lamp, when illuminated, indicates that the instrument is in tune, whilst the two adjacent lamps respond to a count error of between one and sixteen and the outer lamps to an error of more than sixteen

5 citations


Patent
23 Jun 1970
TL;DR: In this paper, a plurality of AND logic gates and OR logic gates are included for converting numbers between positive and negative radices comprising the digits of the numbers to be converted, respectively.
Abstract: Apparatus for converting numbers between positive and negative radices comprising a plurality of EXCLUSIVE OR logic circuits responsive to the digits of the numbers to be converted, respectively. A plurality of AND logic gates responsive to the digits of the even orders of the numbers, respectively, and a plurality of OR logic gates responsive to the digits of the odd orders of the numbers, respectively, are included. Each AND gate and each EXCLUSIVE OR circuit associated with a particular even order is responsive to the output of the OR gate associated with the odd order preceding the particular even order. Each OR gate and each EXCLUSIVE OR circuit associated with a particular odd order is responsive to the output of the AND gate associated with the even order preceding the particular odd order.

Patent
02 Feb 1970
TL;DR: In this paper, logic NAND gate circuits of the type capable of driving a low impedance or a high capacitance load while maintaining relatively fast propagation speed are defined, which include a pair of output transistors of one type respectively connected to bias voltage supplies and connected in common to an output circuit.
Abstract: Disclosed are logic NAND gate circuits of the type capable of driving a low impedance or a high capacitance load while maintaining relatively fast propagation speed which include a pair of output transistors of one type respectively connected to bias voltage supplies and connected in common to an output circuit, and a plurality of input transistors connected between the bases of the output transistors. A logic 1 input signal at any one of the input transistors produces a logic 0 output signal.

Patent
03 Sep 1970
TL;DR: In this article, it is shown how to suppress a proportion of the signal elements in the digital output of the converter and replacing them by signal elements representing digits of a data signal, means being provided to minimize the distortion caused by the introduction of the data signal.
Abstract: 1,203,768. Multiplex pulse code signalling. MINISTER OF TECHNOLOGY. 26 Oct., 1967 [27 Oct., 1966], No. 48184/66. Heading H4L. Telecommunication apparatus includes an analogue-to-digital converter, and switching means for suppressing a proportion of the signal elements in the digital output of the converter and replacing them by signal elements representing digits of a data signal, means being provided to minimize the distortion caused by the introduction of the data signal. As shown in Fig. 1 an input analogue signal is supplied to a delta-modulator 3, the output S of the modulator being supplied to an AND- gate 7, and a data signal T is supplied to an AND-gate 6. The modulator 1 controls a timing circuit 5 consisting of a counter arranged to produce a pulse H at every nth signal element produced by the delta-modulator to open the AND-gate 6 and pass a data signal element T via an OR-gate 9 to the transmission channel 10. At the same time a complementary pulse H closes the gate 7 and blocks the corresponding signal element from the modulator 1. At the receiver a timing circuit 11 similar to circuit 5 is synchronized by known means so that its output H 1 coincides with the received data signal elements to open a gate 12 at the appropriate time. The combined signals are passed to a low-pass filter 13 which smoothes the pulse-coded signals to reconstitute the analogue signal. It is stated that the signal is only slightly degraded since although the feedback circuit 4 of the delta modulator 1 is modified by the insertion of a data signal element, the modulator tends to produce a complementary signal element during the next signal element period which effects some compensation. Compander circuits 14, 15 may be included at the transmitter and receiver respectively. A synchronizing signal for the control of the timing circuit at the receiver may be provided by a frequency divider at the transmitter and consists of alternate " 1 " and " 0 " at every mth signal element, Fig. 3 (not shown). The timing circuits at the transmitter and receiver may be controlled by a quasi-random code signal generator so that the data signal is inserted in a quasi-random sequence, Fig. 4 (not shown). The feedback circuit of the coder in these embodiments may be modified in that it is clamped to a neutral voltage midway between the voltages representing " 1 " and " 0 " when a data signal element is inserted, Fig. 5 (transmitter) and Fig. 6 (receiver) (not shown). In a further modification, Fig. 7 (not shown) a bistable circuit is arranged to introduce into the feedback circuit of the coder a signal element which is the complement of the immediately preceding signal element S whenever a dat a signal element is transmitted. A corresponding g arrangement may be provided at a receiver, Fig. 8 (not shown). In a further arrangement, Fig. 9 (not shown) the output S of the delta modulator is supplied to a chain of four bistable circuits interconnected by gating circuits so that consecutive digits in the output S are registered, permitting the digits immediately preceding and following each data insertion to be examined. When no data insertion is taking place the device acts as a shift register transmitting the digitized analogue signal normally. A data signal to be inserted is gated into the third bi-stable in the chain to replace the normal signal element and the logic is such that if the signal element to be replaced is the same as that inserted no compensation takes place but if it is different and one of the adjacent signal elements is the same then that signal element is inverted. A table giving the various possibilities and compensation effected is included. Alternatively, Fig. 11, compensation is effected at the receiver. The transmitter is similar to that shown in Fig. 1 but the coder feedback circuit is not modified by the inserted data signals. At the receiver the bi-stable circuits 90 to 93 act as a shift register and produce outputs representing the consecutive signal elements and their complements which when the analogue signal is at zero level consist of alternate ones and zeros. When an inserted data signal element arrives at bi-stable 90 the pulse H ceases, closing gate 39, and pulse H1 is applied to gate 96 and via a potential divider 97 to gate 98. When the signal elements A1, A2, A3, A4 immediately preceding a data signal element are 0, 1, 0, 1 respectively, both gates 96, 98 are opened but only the output level at gate 96 is effective as the output of gate 98 is at a neutral level determined by the potential divider 97. Hence a " 1 " is supplied via OR gate 99 to the low pass filter 13 in place of the inserted data element which is blocked by gate 39. If these signal elements A1, A2, A3, A4 are 1, 0, 1, 0 respectively, the gates 94, 95, 96, 98 are closed and a " 0 " signal is supplied to the filter 13. In the cases where the digits A1, A2, A3, A4 do not form an alternating pattern, the gate 94 is closed and gate 95 open and a neutral voltage from the potential divider is supplied to the filter 13.

Patent
31 Dec 1970
TL;DR: In this article, a binary counter is set with the number of one horizontal coordinate for a particular vertical coordinate, and gate stages associated with each stage of the counter receive signals which set them sequentially with the numbers of all horizontal coordinates.
Abstract: A mathematical function having horizontal symmetry is generated progressively for each vertical coordinate. A binary counter is set with the number of one horizontal coordinate for a particular vertical coordinate. Gate stages associated with each stage of the counter receive signals which set them sequentially with the numbers of all horizontal coordinates. When the gate stage number matches that contained in the counter an output signal is produced by every gate stage enabling a first AND gate. The outputs from the gate stages are also inverted to the complementary binary number and enable a second AND gate. The AND gate signals identify the two symmetrical horizontal coordinates associated with the vertical coordinate.

Patent
Cooper Kenneth1
17 Mar 1970
TL;DR: In this paper, a fluidic logic control system for raising and lowering mine roof supports is described, where each unit has a first OR gate which controls a first interface valve to lower and advance itself, a second interface valve causing the support to rebrace itself controlled by a second OR gate interconnected with the first through an AND gate which receives inputs from a sensor denoting that the advance has been completed.
Abstract: Mine roof supports have a fluidic logic control system for raising and lowering the supports and for advancing the supports in the form of a number of units one on each support. Each unit has a first OR gate which controls a first interface valve to cause the support to lower and advance itself, a second interface valve causing the support to rebrace itself controlled by a second OR gate interconnected with the first through an AND gate which receives inputs from the first OR gate and a sensor denoting that the advance has been completed, an AND gate receiving inputs from a sensor denoting that the support is rebraced and from the second OR gate to provide an input for the first OR gate of the next unit and a reset signal which is passed through a delay restrictor to reset the first OR gate of the support.

Patent
26 Mar 1970
TL;DR: In this paper, a scheme for transforming input digital information into output analog information where the output is a specified and not necessarily linear function of the input is disclosed, and the circuitry for achieving this result consists of a ladder network, a waveshaping impedance, and a signal generator connected in series.
Abstract: A scheme for transforming input digital information into output analog information where the output is a specified and not necessarily linear function of the input is disclosed. In its simplest form, the circuitry for achieving this result consists of a ladder network, a waveshaping impedance, and a signal generator connected in series. Each rung of the ladder network is a series impedance and gate circuit associated with a specified digital position in the input code and the corresponding impedance is weighted as a function of its positional significance. An output operational amplifier may optionally be provided which serves to invert and appropriately shift the output signal to achieve the desired output waveform.

Journal ArticleDOI
TL;DR: Experimental and theoretical results on highspeed transformation of analogue information into pulses are presented and designs for three more basic gates, namely, the `Inverter?
Abstract: Further developments of high-frequency pulse and logic elements employing semiconductor bulk-effect devices are presented. Regeneration gain of high values has been achieved. The effects of circuit and device parameters have been investigated. Experimental and theoretical results are presented on a wide range of logic gates `Exclusive OR?, `Inclusive OR?, `AND? and `Inhibitor?. Designs for three more basic gates, namely, the `Inverter?, `NOR? and `NAND? are proposed. Further experimental results on highspeed transformation of analogue information into pulses are presented. A storage loop employing two Gunn devices has been developed.

Patent
18 Mar 1970
TL;DR: In this article, a branch circuit is used to delete or repeat a certain proportion of the input pulses before they can be applied to the counter 2 to convert from one scale of measurement to another.
Abstract: 1,185,037. Electronic counters. RANK ORGANISATION Ltd. 23 June, 1967 [23 March, 1966], No. 12827/66. Heading G4A. Apparatus for converting from one scale of measurement to another comprises a counter 2 responsive to input pulses and a branch circuit 18 responsive to the same input pulses to delete or repeat a certain proportion before they can be applied to the counter 2. As applied to a helium neon laser interferometer, such as described in Specification 1,126,744, which produces a train of pulses representative of the movement of a target, the wavelength of the laser light has to be converted into inches. By losing one pulse in 291 and dividing by 8,000 a very close approximation is achieved. In the branch circuit as counter 18 passes through 291 in forward or reverse direction so one or other NAND gate 21 or 22 operates to close AND gate 16 to an input pulse. The modified count is registered on binary stages 10-12 and decimal stages 13, 14. Conversion to centimeters may be arranged (Fig. 2, not shown) by emitting the first binary divider 10 and having two additive branch circuits feeding in via delay lines to add one pulse in four and one in fifty, respectively. The dividing ratio of counter 18 may be adjusted, step by step, with pressure or temperature which affect the wavelength of the laser beam (Fig. 4, not shown).

Patent
03 Sep 1970
TL;DR: In this paper, a phase shifter is used for phase shifters in a two-dimensional array of modules with a phase shift and phase shift switches, which are associated with switches to produce pulses into quantizers in the ratio 1, 2, 3, 3... 28.
Abstract: 1,204,342. Aerials. TEXAS INSTRUMENTS Inc. 30 Aug., 1967 [25 Nov., 1966], No. 39704/67. Heading H4A. In a phased aerial array, each element in a line thereof is fed from separate selectively variable delay means controlled by a counter having outputs of differing orders and corresponding in number to the number of elements in the line, and clock pulses are applied during a time gate proportional to the desired angle of radiation. The embodiment utilizes a twodimensional array of modules (14, Fig. 1) similar to the kind described in Specification 1,124,266. Each module includes a phase shifter 31, Fig. 4 having delay sections 100 . . . 103 in an R.F. path, and being selectively brought into circuit by corresponding switches 104 ... 107; the switches are energized from a counter 111 fed from the point y, Fig. 5. Azimuth and elevation time gate pulses are fed in at respective terminals 133, 134 to AND gates which are fed also at terminal 132 with clock pulses. Azimuth and elevation respective binary circuits 135, 136 (decsribed with reference to Fig. 6, not shown) are associated with switches to produce pulses into " quantizers " in the ratio 1, 2, 3 ... 28 (the aerial array being formed from a 28 by 28 matrix of elements), and the quantizers count down by a factor of 8. Each counter 111, Fig. 4 is associated with a different output of a NAND gate matrix 140, Fig. 5. Voltages on lines 146, 147 determine whether a beam is to be switched left or right of boresight (the magnitude of the beam deflection being determined by the width of the pulse applied to terminal 133) and similarly for beam deflection above and below boresight. A diagram of the switches and quantizers is described, Fig. 7 (not shown). A modification is described, Figs. 8, 9 and 10 (not shown).

Patent
04 Mar 1970
TL;DR: In this paper, a phase discriminator has an output comprising pulses of a width corresponding to the phase error, and these pass to unit 11 where they are used to gate clock pulses passing from the source 18 to the counter 10.
Abstract: 1,183,227. Automatic phase control systems. INTERNATIONAL STANDARD ELECTRIC CORP. 28 July. 1967 [19 Aug., 1966], No. 34811/67. Heading H3A. An automatic phase control system includes means for storing the phase error and producing from the stored signal a replica of the output of the phase discriminator for use if the supply of reference signal is interrupted. In Fig. 1 the phase discriminator 2 has an output comprising pulses of a width corresponding to the phase error, and these pass to unit 11 where they are used to gate clock pulses passing from the source 18 to the counter 10. The count stored in the counter 10 therefora corresponds to the current phase error, and is used to select, from waveforms produced by units 13-15 and 17, a waveform corresponding to the stored count and approximating to the output waveform of the discriminator 2. Normally AND gate 6 is open and gate 5 closed, but if the signal form the reference source 3 is interrupted a detector 9 reverses the condition of the two gates to allow the waveform from unit 13 to pass through the low pass filter 4 to control the oscillator 1. Each sampling cycle is preceded by a reset pulse from unit 19 which resets counter 10, and by a timing signal from source 12 which enables the gating unit 11.

Patent
William K. Hoffman1
28 Jan 1970
TL;DR: In this paper, a circuit has a field effect transistor (FET) with source, drain and gate electrodes, and a capacitor connecting the source and gate electrode is provided for applying a sufficient pulse to the source electrode and through the capacitor to the gate electrode to give an output signal at the drain electrode independent of any signal information which may be stored on the gate.
Abstract: A circuit has a field effect transistor (FET) with source, drain and gate electrodes, and a capacitor connecting the source and gate electrode Means is provided for applying a sufficient pulse to the source electrode and through the capacitor to the gate electrode to give an output signal at the drain electrode independent of any signal information which may be stored on the gate electrode

Patent
15 Apr 1970
TL;DR: In this article, the authors present a digital transmission system where synchronizing signals are derived from a signal which has digital data signals at times tn, t 1 n and non-significant signals at all other times.
Abstract: 1,187,688. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 10 Oct., 1968 [8 Nov., 1967; 9 Nov., 1967; 8 Dec., 1967], No. 47975/68. Heading H4P. Synchronizing signals are derived from a signal which has digital data signals at times tn, t 1 n and non-significant signals at all other times. Whenever the signal has a preset amplitude a sync. pulse is generated. This amplitude occurs at tn, t 1 n and may also occur at other times. The receiver prevents sync. pulses occurring at times other than tn, t 1 n from effecting the oscillator. In one embodiment, the received signal contains binary data and passes to a subtraction unit S, Fig. 3, via rectifiers 31, 32 and delay 33 whose period t = t 1 n-tn. The output of S is a signal which has zero amplitude whenever the preset amplitude is detected, and is passed via monostables SS1, SS2 and inverter I1 to OR gate 01 which gives pulses p whenever the output of S is zero. Gate 01 feeds oscillator Plo which clock pulses of period T, T being the recurrence period of both tn and t 1 n. Gate A1 is inhibited by the output of monostable SS3, fed by the clock pulses, so that any sync. pulses occurring at times other than tn, t 1 n cannot reach Plo. During unitial synchronization, when a special start signal is received, a signal on Dem maintains A1 enabled. In a second embodiment, Fig. 5 (not shown), the digital signals may take any of four preset valves. Rectifiers 31, 32, Fig. 3, are additionally connected to two weighted subtraction units whose outputs pass to an EXCL-OR gate which feeds a second EXCL-OR gate inserted between S and SQ: Another arrangement, Fig. 6, in which there is no initial sync. signal, uses a series of delay units, each of period T, to which the rectified received signal is fed. An AND gate, A3 is fed as shown and emits a pulse about the times tn, t 1 n, Fig. 2b (not shown), since at other times at least one input to the gate is likely to be zero. The output of the gate is used to gate appropriate pulses of signal p to the oscillator. Alternatively, Fig. 7 (not shown), the delays may be replaced by a single delay T fed via an AND gate with the rectified signal, the delay giving synchronizing pulses which are also fed back to the gate. The delay may comprise a shift register, and a threshold unit may precede the AND gate, Fig. 8 (not shown). In another embodiment, Fig. 11, there is a unit 111 generally similar to Fig. 3, and in addition a weighted adder 112 and a unit 113 containing an adder, a delay, and a subtractor. The outputs of both 112 and 113 are zero only about tn, t 1 n, and are fed to analog adder AD3 together with the clock signal from PL0. The resulting signal c is zero at times t 1 n and attenuates the unwanted pulses from 111, the wanted pulses synchronizing the oscillator PL0. Where 4-level signals are received, Fig. 13 (not shown), units 112, 113, Fig. 11, are replaced by weighted adders Ad4, Ad5, the lesser of the two outputs passing to the gate Ad3. In a final embodiment, Fig. 15, the received signal is fed direct and via a delay t to a unit 151, which outputs the lesser of the two signals. This output passes to capacitor C1 to Cn, switched in sequentially for a period T/n by unit Seq. A capacitor charges slowly when switched in unless the output of 151 is zero, when the capacitor rapidly discharges. Since 151 gives zero output at random, but never at the times t 1 n, after several periods T one capacitor will have a charge higher than the others, so identifying the time t 1 n.

Patent
24 Jun 1970
TL;DR: In this paper, a four-layer control rectifier is designed to handle very high power in the period immediately following ignition by ensuring that the distribution of gate current is widespread and uniform.
Abstract: 1,195,998. Thyristor circuits. ALLM€NNA SVENSKA ELEKTRISKA A.B. 30 Oct., 1967 [31 Oct., 1966], No. 49159/67. Heading H3T. [Also in Division H1] Controlled rectifiers (exemplified by fourlayer structures) are designed to handle very high power in the period immediately following ignition by ensuring that the distribution of gate current is widespread and uniform. To do this, both emitter and gate electrodes are provided on the emitter region but are separated by a high-resistance zone of uniform properties. (In the structure shown, high conductivity surface material is removed from the emitter region to leave a high-resistance zone at the bottom of a groove 8.) In variants several highresistance zones may be formed to separate parts of the emitter region which are each provided with a gate or emitter electrode. The gates and emitter are respectively strapped together, either directly or through current dividing impedances. To obtain the desired characteristics a high firing current is needed. This is provided by auxiliary thyristor 21 which may be formed in the same semi-conductor body as the main rectifier. When the auxiliary thyristor is fired by the closure of switch 22, the voltage drop across impedance 20 produces the necessary firing current in the main rectifier. (For structural detail, see Division H1.)

Patent
24 Jun 1970
TL;DR: In this paper, a frequency comparator for evaluating the difference between the frequencies of two pulse signals applied on lines X, Y comprises gating means G4, G5 controlled to block, on each line, the first pulse and pass each subsequent pulse of a series arriving on the line uninterrupted by a pulse on the other line, and means G6 for combining the pulses passed along the two lines.
Abstract: 1,196,102. Frequency comparators. KEELAVITE HYDRAULICS Ltd. 26 Feb., 1969 [1 Feb., 1968], No. 5163/68. Heading H3A. [Also in Division G3] A frequency comparator for evaluating the difference between the frequencies of two pulse signals applied on lines X, Y comprises gating means G4, G5 controlled to block, on each line, the first pulse and pass each subsequent pulse of a series arriving on the line uninterrupted by a pulse on the other line, and means G6 for combining the pulses passed along the two lines. The gates G4, G5 are controlled by a bi-stable circuit FF, the inputs of which are coupled to points on the lines. Assume initially bi-stable FF is in its " set " state, closing gate G4 and opening gate G5. If a pulse occurs on line X this will not pass through gate G4, but will reset bi-stable FF to open gate G4 and close gate G5. If the next pulse to occur is on line X it will pass through gate G4 to the output. If the next pulse is on line Y it will be inhibited by gate G5, but will again set bi-stable FF to open G5 and close G4. Thus if the two frequencies are the same, no pulses are fed to the output. If the frequency on line X is greater than that on line Y, the bi-stable FF will be mainly in its reset state and gate G4 will pass the X line pulses to the output, with the exception of the first X line pulse to follow a Y line pulse. If the Y line frequency is the greater, the converse will obtain, with the bi-stable being mainly set. The outputs from the two gates are combined in OR gate G6 and fed to a counter (not shown) which counts forwards or backwards depending on the state of bi-stable FF. In order to prevent simultaneous signals arriving at gates G4, G5 further gates G2, G3 are provided which are inhibited by AND gate G1 if simultaneous signals occur. The input signals are suitably shaped by triggers VST1, VST2 and monostables S1 S2, S3, S4. The circuit may be formed from NAND, NOR logic, Fig. 2 (not shown). The comparator is used in a motor speed control system (see Division G3).

Patent
04 Mar 1970
TL;DR: In this paper, a digital indication of position is derived from a track 10 formed from a number of portions of equal length alternate ones having different characteristics to represent "1" and "0", detectors 16 and 17 spaced apart by half a portion length (or the equivalent) and providing first and second binary signals controlling a binary counter 18 having a numbers of stages 19, 20, 21 connected by gates 23-26 so as to count in Gray Code.
Abstract: 1,182,678. Digital indication of position. DECCA Ltd. 14 Nov., 1968 [21 Nov., 1967], No. 52962/67. Heading G4H. A digital indication of position is derived from a track 10 formed from a number of portions of equal length alternate ones having different characteristics to represent "1" and " 0 ", detectors 16 and 17 spaced apart by half a portion length (or the equivalent) and providing first and second binary signals controlling a binary counter 18 having a number of stages 19, 20, 21 connected by gates 23-26 so as to count in Gray Code. The portions, as described, are alternately translucent and opaque and are sensed by photo-cells 16, 17. Conductive and non-conductive portions may be used instead. The signals from detector 16 are applied directly to bi-stable 19 while those from detector 17 are differentiated at 22 and applied to gate 24. The bi-stables 19-21 have set and reset outputs Q and Q. The set output Q is applied to AND gate 23 with the output of the differentiator 22, so that if bi-stable 19 is set, bi-stable 20 is changed when the detector 17 passes from a " 1 " to a " 0 " portion or vice versa. The change signal from the differentiator can only pass to the next stage if the bi-stable 19 is reset and the signal Q is present at the gate 24. With this arrangement the counter counts in Gray Code forward and backward depending on the direction of movement of the member 10. The apparatus may be used to position a chart in accordance with signals from a computer representing for instance the position of a mobile craft. The chart is driven until the signals derived from the counter compare with those from the computer. An extra track parallel with the first track may provide parity check bits. Specification 1,176,556 is referred to.

Patent
03 Sep 1970
TL;DR: In this paper, the motor voltage is applied to transformer PT having a centretapped secondary winding supplying opposed signals A, A1 to differential amplifier DA1 for generating square-wave pulses B, B1 to a gate AND 1.
Abstract: 1,204,148. Control of A.C. motors TOKYU SHARYO SEIZO K.K. 29 Nov., 1967, No. 54424/67. Heading H2J. The loading condition of an A.C. motor which drives a machine tool, is detected as a variation in the power factor of the motor, the tool being retracted, or its feeding speed reduced, if the load becomes excessive. The motor voltage is applied to transformer PT having a centretapped secondary winding supplying opposed signals A, A1 to a differential amplifier DA1 for generating square-wave pulses B, B1 to a gate AND 1. The output of the gate is in the form of pulses C which occur at each zero passage of the supply voltage. A current transformer CT is similarly associated with a differential amplifier DA2 and gate AND 2, the pulses F occurring at each zero passage of the motor current. The signal C is supplied through a delay circuit PD to a multivibrator MM whose square output waveform E has a predetermined width. The signals E and F are applied to gate AND 3 which supplies a signal to store BM provided that the pulse F occurs during the period of the pulse E indicating that the load on the motor is excessive. The output from the store is fed to element MCA for controlling the cyclic operation of the machine, the store being reset after each cycle of operation of the machine. If the motor becomes overloaded the unit MCA is conditioned to take the safety measures referred to above.

Patent
20 Apr 1970
TL;DR: In a three-dimensional current coincident mode memory plane, inhibit lines, common-inhibit-sense lines and/or sense lines are divided into a plurality of pairs of wirings so as to be selectively driven through an address decode matrix by drivers and gate switches.
Abstract: In a three-dimensional current coincident mode memory plane, inhibit lines, common-inhibit-sense lines and/or sense lines are divided into a plurality of pairs of wirings so as to be selectively driven through an address decode matrix by drivers and gate switches

Patent
15 Apr 1970
TL;DR: In this paper, an ultrasonic presence detector was proposed for detecting vehicles in the presence of an object in an observation zone with respect to the change in transit time of pulses of ultrasonic energy transmitted by a transmitting transducer towards and reflected by a reference surface.
Abstract: 1,187,775. Detecting objects acoustically. MARCONI CO. Ltd. 24 April, 1967 [21 June, 1966; 23 Aug., 1966], Nos. 27712/66 and 37838/66. Heading H4P. In an ultrasonic presence detector of the kind which is responsive to the change in transit time of pulses of ultrasonic energy transmitted by a transmitting transducer towards and reflected by a reference surface when an (reflecting) object enters the path between the transducer and the reference surface, a predetermined responded condition is produced when such object is present and this condition is changed only on receipt of a reflected echo from the reference surface. Thus, in ultrasonic traffic detectors in which the reference surface comprises the road surface and the object comprises a vehicle, spurious indications that a vehicle has left the observation zone is prevented when, e.g. the vehicle includes a portion which is absorbent or dispersive for ultrasonic energy such as a commercial vehicle carrying a load of hay or gravel respectively. Fig. 1 shows the embodiment in which a pulse generator 2 producing pulses of 2 millisecond duration with a repetition rate controlled by a free-running multivibrator 4 energizes an ultrasonic transmitter, the pulses from which are reflected either by a road surface 3 or by a vehicle 7 (if present) and received by an ultrasonic receiver 5 the output of which is supplied via an amplifier 9 to two threshold trigger circuits 110, 210, which provide outputs fed via respective amplifiers 120, 220 to respective gates 21, 22. These gates are opened by the outputs of respective timing circuits 13, 14 forming part of a chain of timing circuits 12-15 the first, 12, of which is triggered by the same edge of the output uniform of multivibrator 4 that triggers pulse generator 2 and the output of each circuit triggering the next circuit. Gate 21 which is controlled by timing circuit 13 to open shortly after generator 2 is triggered, to prevent signals picked up by direct transmission or by break-through, from being passed, is closed shortly before the expected time of arrival of a pulse reflected by the road surface. When gate 21 closes timing circuit 14 opens gate 22 which remains open until after the expected time of arrival of a road reflected pulse. Thus when reflected pulses received by receiver 5 are supplied to gates 21, 22, threshold circuit 110 eliminating spurious signals due to reflections by cyclists, pedestrians &c. and threshold circuit 210 being adjusted to pass round reflected pulses, vehicle reflected pulses are passed by gate 21 and road reflected pulses by gate 22 to respective bi-stable circuits 23, 24. The latter circuits are "set" by the outputs of gates 21, 22 and remain in this condition until "re-set" by a pulse on lead 31 at the instant that generator 2 is triggered. When circuit 23 is "set" by a vehicle reflected pulse it supplies an output which "sets" a further bi-stable circuit 25 the polarity on the output line 27 of which is reversed and this polarity which forms the predetermined responded condition (indicating the presence of a vehicle) is supplied to utilization means such as a counter 30. The "set" output of circuit 23 is also supplied to a gate 29 which is opened only for a very short period (determined by timing circuit 15) following the expected time of arrival of a road reflected pulse and gate 29 therefore, only supplies an output if, following the resetting of circuit 23, circuit 24 is "set" by a road reflected pulse. The resetting output of gate 29 on lead 28 then "resets" circuit 25 and terminates the predetermined responded condition. Means may also be provided for utilizing the time of arrival of pulses passed by gate 21 to provide an indication of the height of the vehicle and further means may be provided for utilizing the duration of the output of the predetermined responded condition of circuit 25 to provide an indication of vehicle lengths, or, if this is known, of vehicle speed. The frequency of multivibrator 4 may be adjusted by switch means which selects appropriate time constant determining resistors to permit the apparatus to be operated with the transducers at different heights above the road surface. In order to compensate for changes in the amplitudes of reflected signals when the height is changed the effective threshold response of circuits 110, 210 is adjusted by an adjustable feed-back loop across amplifier 9 comprising a set of different resistors selected by a switch ganged to the switch which selects the time-constant determining resistors for the multivibrator (Fig. 2, not shown).

Patent
Paul Abramson1, Gerald Goertzel1
18 Dec 1970
TL;DR: In this article, a low-pass filter is connected to each of the outputs of the AND gates associated with each tone, and then it is determined whether the output of any of the analogue OR gates exceeds a standard value.
Abstract: A parallel tone detection method, system and apparatus includes using several generators for providing square waves at the fundamental frequency of several parallel tones to be detected. An unknown input signal is clipped and then AND gates are used to test for the simultaneous presence of the A.C. polarities of both the unknown input signal and each respective square wave. A low-pass filter is connected to each of the outputs of the AND gates associated with each tone. The outputs of the filters for each tone are connected into a corresponding analogue OR gate, which is one of a series of analogue OR gates. Then it is determined whether the outputs of any of the analogue OR gates exceeds a standard value. If it does then a circuit determines which analogue OR gate produces the largest output to identify the tone received.

Patent
02 Apr 1970
TL;DR: In this paper, a percussive welding apparatus for welding a lead 10 to a stud 11, Fig. 1, comprises a spring-urged chuck 12, and a circuit including a battery 14, resistors 15, 17 and a capacitor 16.
Abstract: 1,186,231. Percussive welding. WESTERN ELECTRIC CO. Inc. 3 May, 1967 [6 May, 1966], No. 20425/67. Heading B3R. Percussive welded joints are rejected when the welding current waveform peaks at a value above or below a predetermined range of values during the shrinking of the arc, and also if current transients dip below an empirically determined amplitude for longer than a predetermined period. A percussive welding apparatus for welding a lead 10 to a stud 11, Fig. 1, comprises a spring-urged chuck 12, and a circuit including a battery 14, resistors 15, 17, and a capacitor 16. Optimum, or ideal voltage, current, and impedance, curves are plotted against welding time in Fig. 3, and the relative positions of lead 10 and stud 11 at these values are shown. Fig. 4 (not shown), comprises an ideal current waveform which peaks within an acceptable range of between 150 and 200 amperes. Fig. 5 (not shown), comprises the current waveform of an unsatisfactory weld, in which the waveform peaks above this range, and in addition there are current transients which dip below a predetermined amplitude, and remain there for longer than the predetermined period. A block diagram of an apparatus for carrying out the method, is shown in Fig. 6. Assuming a 100 ampere threshold for the welding current, a detector 20 is energized by the current, produces a signal, and triggers a pulse generator 21. A 50 millisecond pulse enables an OR gate 22 to operate for a 50 millisecond period, which is longer than the welding cycle. A pulse generator 24 is operated by detector 20 through a time delay 23, and the generator produces a one millisecond positive pulse window 19, Fig. 5 (not shown). Generator 24 simultaneously applies a one millisecond pulse 25 through a time delay 26 to enable an AND gate 27. Pulse 19 is applied to a comparator 29, along with a voltage signal, which follows the welding current input, and is supplied by an amplifier 30. If the waveform dips into window 19, comparator 29 produces a voltage signal which is integrated in an integrator 31. If the waveform does not remain continuously in window 19 for more than 200 micro seconds, the output of integrator 31 will not rise above zero volts, and a detector 32 will not be triggered. If, however, the time is 200 micro seconds or more, detector 32 is triggered and produces a signal which is gated through the enabled OR gate 22, and energizes a reject relay RY1, which operates means for indicating to the operator that the weld is unsatisfactory. Relay RY1 is also energized if the welding current peak is greater or less than the predetermined amplitude range, and this is determined after a time delay provided by a time delay circuit 26, by comparators 34, 35. If the peak is incorrect, AND gate 27 will receive a voltage signal from one of the comparators 34 or 35. This signal will remain on the input lead of gate 27 until pulse 25 enables the gate, approximately two milliseconds after the OR gate 22 is enabled by generator 21, and approximately 100 micro seconds after the trailing edge of window 19 is formed. If gate 22 is gated by a pulse from gate 27 it will energize reject relay RY1, so as to indicate that the weld is unsatisfactory. If the welding current waveform has a peak which falls in the acceptable amplitude range, and also does not dip into window 19 and remain therein for 200 micro seconds, OR gate 22 will not pass a signal, and after a predetermined period established by a time delay 38, an accept relay RY2 will be energized to indicate that the weld has passed both tests.