Showing papers on "AND gate published in 1976"

F/LOGIC - An interactive fault and logic simulator for digital circuits

Abstract: Digital simulators are becoming a standard and necessary CAD tool in the circuit design process. The acceptance of this design aid is a result of a number of factors, the predominant one being the over-whelming size and complexity of present day logic circuits and the requirement that a complete test plan be developed for these circuits. Another factor is that recent generation logic simulators have proven to be very flexible tools, capable of simulating very large circuits with a high degree of precision.

Complementary mos logic circuit

Abstract: A dynamic complementary metal -oxide-semiconductor circuit (CMOS) includes a pair of gate stages connected in cascade. The first gate stage includes a first logic block which effects a prescribed logical function, the logic block being connected between a P-type and the N-type MOSFET. The source electrodes of the P-type and the N-type MOSFETs are connected between a power supply and ground, respectively, and their gate electrodes are connected in common. Moreover, the first gate stage has its output terminal connected to a load capacitor. The second logic block is also connected between a P-type MOSFET and an N-type MOSFET. The source electrodes of these MOSFETs are connected between a power supply and ground, respectively, while the gate electrodes thereof are connected in common. Also, a second load capacitor is connected to the output of the second gate stage. A pair of pulse signals, inverted with respect to each other, are applied to the first and second gate stages for driving the same, respectively. One of the MOSFETs making up the second logic block is of the type and is connected so that, when the power supply voltage applied to the gate thereof from the first gate stage, that MOSFET is turned "off". As a result, the possibility of misoperation due to the decrease in the charge of the first load capacitor, at the output of the first gate stage, is prevented.

Logic circuit arrangements using insulated-gate field effect transistors

Abstract: A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Abstract: As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with31P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by31P and11B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with31P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm2.

Display enhancement technique for video moving trace display

Abstract: A system providing a substantially gapless continuous line display of an analog signal as a function of time on a television monitor. The input is digitized and each level of quantization corresponds to one of the raster display lines to give proper vertical deflection. During each line of raster scan an oscillator and counter sequence the input address to a memory through a desired number of horizontal sampling positions, requiring an address of the order of 8 bits. Each address gives an output of several bits giving in digital form the instantaneous y coordinate of the signal. This is digitally compared with the digitized associated raster line number in a first digital comparator. This is also stored in a register strobed from the above-mentioned counter just before each change of address. The raster line number and the stored previous output are digitally compared in a second digital comparator. If the line number is less than the current trace deflection but greater than the previous deflection, a first AND gate provides an output signal at that instant. Similarly, if the line number is greater than the current trace deflection but less than the previous deflection, a second AND gate provides an output signal. If the current deflection is equal to the line count, this also provides a signal. An OR gate receives these signals, and any one of them will provide a trace-brightening signal at the output of the OR gate. The "equal output" signal is delayed by a time corresponding to 1/2 the horizontal sampling interval to improve the horizontal resolution.

Field effect transistors

Abstract: A field effect transistor includes a thin silicon layer formed on a sapphire substrate and having source, gate and drain regions. A buried layer of the same conductivity type as that of the gate region and a higher impurity concentration than that of the gate region at the lower portion of a junction between the source and gate regions.

Optical recorder/reproducer

Abstract: PURPOSE: To prevent the occurrence of double recording by detecting the light transmitting through or reflecting from a disc and controlling a recording gate circuit depending upon the presence or not of reproduction signal. CONSTITUTION: A disc 15 is radiated by the laser light from a laser 1 and the transmitted light is detected with photoelectric detectors 8a, 8b. The voltage corresponding to the reproduction signal is detected through an amplifier 101 and LPF 102 and is then compared with a reference voltage in a comparator 103, whereby the presence or not of the reproduction signal is detected. In case there is the reproduction signal, and FF 105 is set by the output of the comparator 103 and an AND gate 106 is closed by the set output of the low level of the FF 105, thus the revolution detection signal generated at each one revolution of the disc 15 outputted by a revolution phase detector 15 is not applied to the gate circuit 21. Since the gate of the circuit 21 is not closed, the recording singal is not applied to a photo modulator 2 even if the recording switch of the circuit 21 is inadvertently turned ON. Hence, the occurrence of double recording is prevented. COPYRIGHT: (C)1979,JPO&Japio

Land mine detector with pulse slope, width and amplitude determination channels

Abstract: Circuitry for detecting buried non-metallic and metallic land mines is diosed. A peak detector receives signals from a conventional search head. The output of the peak detector is amplified and this amplified signal is applied to a slope determination channel, to a pulse width determination channel and to a pulse amplitude determination channel. The output pulses from the slope determination channel, the pulse width determination channel and the pulse amplitude determination channel are all applied to different inputs of an AND gate. If pulses are coincidently present on all the inputs of the AND gate, the AND gate provides an output pulse which is applied to a field effect transistor (FET) switch. The FET switch controls the gain of an amplifier such that the gain of the amplifier is measurably increased when the AND gate applies a pulse to the FET switch. When the gain of the amplifier is increased by the FET switch, a signal burst indicating that a mine has been detected is produced on the output of the amplifier. The output from the amplifier is typically coupled to a headset worn by the person conducting the search.

Collector-up logic transmission gates

Abstract: Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal. Gate switching means is connected between said gate logic node and said gate control input, said means being responsive to first and second logic levels at said gate control input for driving said gate logic node to first and second states causing the transmission gate to assume open and closed states from input to output. A bidirectional bipolar logic transmission gate includes an additional gate logic node and gate switching means simultaneously drives said gate logic node and additional gate logic node to first and second states causing the transmission gate to assume bilateral open and closed states between said first and second input and output terminals.

Solid state timer-stepper with soft switch-on and switch-off load control

Abstract: A timer-stepper, which is particularly applicable to light chasers for producing a special "ripple" lighting effect and increasing bulb and logic circuit component lives, having photoncoupler phase-shifting networks in the gate circuits of switching triacs for "softness" during switching and for isolating the logic of said timer-stepper from A.C. line or switching transients.

Bit-slice type large scale integrated circuit with multiple functions on a one-chip semiconductor device

Abstract: Various kinds of control circuits and gate circuits are integrated on a one-chip semiconductor device to make up a bit-slice type large scale integrated circuit (LSI) with multiple functions. The gate circuits are connected with the control circuits for selecting input and output signal lines. Selecting signals are supplied to the gate circuits through the selecting lines. The gate circuits select the connection between the control circuits and the input and output lines in response to the selecting signals. The one-chip semiconductor device is particularly efficient in that it provides multiple functions without increasing the number of required terminals pins thereof.

Detector device for converting A.C. inputs to an D.C. output and a system for using the same

Abstract: An input detection circuit to provide a D.C. output signal of a selected value upon receipt of an input A.C. signal of a given value on an input line. The detector circuit includes a NORTON type current responsive operational amplifier having an inverted input terminal, a non-inverted input terminal and an output terminal. A circuit is provided at the inverted terminal for biasing the amplifier to provide an output voltage on the output terminal substantially less than the selected output signal. A full wave rectifier connected to the input line and having a first output conductive during the negative portion of an A.C. signal applied to the input line and a second output conductive during the positive portion of an A.C. signal applied to the input line. There is provided a first resistor for connecting the first output of the rectifier to the inverted terminal and a second resistor for connecting the second output to the non-inverted terminal. In addition, there is a system for detecting the existence of concurrent A.C. inputs from at least one of each of two groups of A.C. inputs using the detector device as described above to produce input signals to an AND gate means. The output of this AND gate means can be used to energize devices responsive to the condition indicated.

Field effect transistor and method of construction thereof

Abstract: A field effect transistor and method of making the same wherein a semi-conductor layer is placed on an insulating substrate, and wherein the gate region is separated from source and drain regions of a like conductivity type to that of the source and drain regions but of reduced conductivity, the gate electrode and gate region of the layer being of generally reduced length, and the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Phase logic demodulator

Abstract: A demodulator for a biphase or quadriphase shift-keying system. The demodulator includes two AND gates for biphase demodulation. The AND gate is one which will provide an output signal if and only if the two input signals are in phase. Each of the AND gates forms a feedback with an injection locked oscillator. Therefore depending on the phase of the input signal, one or the other AND gate provides an output which is then injected at the proper phase into the injection locked oscillator. The output of the AND gates is fed to a data logic and envelope detector to recover the data. For quadriphase phase-shift keying, four AND gates are required. The circuit can be constituted either by transistors or by transferred electron devices sometimes called Gunn effect devices.

Control system for an electronic music synthesizer

Abstract: A control system for an electronic music synthesizer includes a circuit responsive to the keying of a musical instrument for producing a binary coded signal. This signal is converted to an analog signal, for application to a music synthesizer. The analog voltage may be modified, for transposition or for portamento effects. The coding circuit may produce trigger and gate voltages for the synthesizer, whereby blowing of the musical instrument, if a wind instrument is employed, is not necessary. Alternatively, the trigger and gate pulses for the synthesizer may be developed from the output of the transducer coupled to the instrument.

Conditional latch circuit

Abstract: A conditional latch circuit is selectively operable as a latch or as an OR gate. The circuit comprises an OR gate having at least three inputs, each connected to the output of separate ones of three AND gates. A fourth AND gate has an inverted output connected to an input of two AND gates and a non-inverted output connected to an input of the third AND gate. The output of the OR gate is connected to a second input of the third AND gate. With one input of the fourth AND gate connected to a binary clock source, the circuit will operate as a latch to store binary signals received at the second input of the first and second AND gates when the second input of the fourth AND gate is connected to binary one. When the second input of the fourth AND gate is connected to a binary zero, the circuit will operate as an OR circuit.

Avalanche memory triode and logic circuits

Abstract: A semiconductor controlled avalanche triode operableat microwave frequencies is turned on by a narrow pulse, and remains conducting due to the positive feedback effect of returning carriers in the base region until turned off by an opposite polarity narrow pulse. Applications include a fast switch, a memory device, and various logic circuits such as logic gates and shift registers. The memory and logic devices are fast, require low power, available in npn or pnp configurations, are simple with one triode per memory, and can be made of silicon so as to be integrable.

Injection logic arrangements

Abstract: A logic flip flop arrangement wherein each of the two outputs of the flip flop has an output gate associated therewith, wherein an input of each of the output gates is connected to an output of a driving gate, and wherein at least one of the output gates has an output thereof combined with an output of that one of the driving gates which is associated with the other output gate to provide a logic function.

Constant current supply with output and polarity selection - using transistor constant current generators and logic inputs

Abstract: The network provides a number of constant current outputs, which may be selected by logic input signals and which may be of either polarity according to an input signal. The network consists of a number of almost independent circuits each of which constitutes a constant current generator with a double transistor output, the polarity being determined by which of these transistors is conducting. The transistors (T1n, T2n) are of opposite types and are connected via their collectors to the relevant output (In). A current generating circuit, consisting of a linear amplifier comparator (V1n, V2n) and an emitter resistance (R1n, R2n), provides constant current from the appropriate collector if it is selected. The selection is by means of logic gates (GUn, GSn), the inputs to which are provided by a single flip-flop (5) for the whole network, and by individual selection signals.

Trigger generator circuit for controlled rectifier - is designed to use logic techniques to control timing of gate voltage and includes opto electric diode

Abstract: A control and trigger circuit is used for gate controlled rectifiers, particularly those used in oscillators where the triggering level and timing are a function of the load state The input trigger is fed to the circuit via an optoelectronic diode-transistor pair (12, 17) The output of which provides one input to an AND gate The second input is derived from a comparator The two inputs to this are a reference level and a voltage which is a function of that across the controlled rectifier The rectifier trigger electrode is driven from the logic output via an emitter follower and current limiting resistor and is itself shunted by a series chain of a resistor, diode and capacitor

Input setting type programming relay

Abstract: The input setting type programming relay is provided with a plurality of input terminals for receiving a binary signal, a memory device connected to the input terminals and presettable with signals 1 and 0 corresponding to respective digits of the binary signal and an AND gate circuit connected to the output of the memory device for producing an ON or OFF signal when the signals set in the memory device coincide with the data of respective digits of the input signal.

Noise elimination method from signal frequencies - is based on auto-correlation principle, with cyclic scanning of received signal polarity

Abstract: The signal is converted in a series of binary signals (S), and the non-delayed signal series is multiplied in an AND gate (5), by a binary signal series (S') which is derived from the first series of signals. It is delayed in a shift register; one of the binary signal series is negated and binary signals delivered by the gate are added in a reversible counter with its reading limited at the lower end by the value zero. The counter is interrogated with a threshold. The scanning frequency is at least twice as high as the highest transmitted frequency and it can be varied during operation.

Method of manufacturing junction type field effect transistors

Abstract: PURPOSE:To form longitudinal, multi-channel VFET so that its gate series resistance is small, the withstand voltage between the gate and source is large and the channel width and gate length are controlled with ease

Pulse value convertor for electricity meters - pulses corresponding to mains voltage and load current converted through matching elements

Abstract: The pulses are converted through matching elements and a power measuring unit, so that a ratio W = Zx/Nx is realised. The pulse value is at first divided in a binary divider (10) with an adjustable contact set (B1) in the ratio 1/N1, then applied to the input of an AND gate (13), and also through an invertor (11) to a decimal counter (12), from which the pulses are applied through an adjustable contact set (B2Z) to the clock pulse input of a flip-flop (14), and through a second adjustable contact set (B2N) for the numerator N2 to the R input of the flip-flop (14), and to the R input of the decimal counter (12). Flip-flop (14) output is connected to the AND gate (13) second input, so that pulses of value W = Zx/Nx = (1/N1). (Z2/N2) appear at the gate (13) output.

Resettable monostable flip-flop - has two monoflops and gates allowing resetting same channel as used for input pulses

Abstract: The resettable monostable flip-flop circuit has the input signal line (a) coupled to the input of a first gate (5), to the input of a second gate (4) and over an inverter (3) to the input of a second monoflop ((2). The first gate output is connected to th input of a first monoflop (1)is connected to the reset input of the first monoflop. The second monoflop output is connected to the second gate second input and over an inverter (6) to the first gate second input. The output of the frist monoflop forms the circuit output. The advantage lies in the circuit ability to pass the reset pulse over the same channel as is used for the input pulses of the same polarity.

Directional logic circuit for electronic electricity meter - delivers pulses whose frequency is proportional to electric power

Abstract: The pulses from the directional logic circuit pass through an AND gate for drawn and delivered energy, and are counted in corresponding separate counter. The measured variable voltage is applied after passing through a matching element to a comparator, whose output is applied through a differentiating element to the clock pulse input of a bistable D-flip-flop. The measured variable current is also applied after passing through a matching element to a differentiating element, whose output is connected to a comparator. The output signal of the latter prepares flip-flop data input. The flip-flop outputs control the AND gates in accordance with the energy direction of flow.

Combined electro optical and wrapped back wiring connections - using layout which can accommodate both and can also perform certain logic operations electronically

Abstract: A system of wiring connections is used in which a combination of electro optical fibres and thin transducers are wrapped joint or other types of connection are available. The chassis layout associated with each row of printed cards consists of a lower part on which pairs suitable for electrical connection are provided, whilst the upper part can accommodate optical fibres and their transducers. This is done by having a slightly projecting accommodating a glass fibre (20) are situated. At the ends of these fibres, mounted in the projecting mounting blocks are transducers clamped firmly in place. These can be either transmitters or receivers. In either case, an electrical connection is also available, so that for example a receiver, an electrical connection, and a transmitter can all be accommodated in one block. Various possibilities arise from this of performing simple logic operations using these connections, and an AND gate and an OR gate are described.