Showing papers on "AND gate published in 1978"

MA-4 the prospects for ultra-high speed VLSI GaAs digital logic

Abstract: Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).

Current-voltage characteristics, small-signal parameters, and switching times of GaAs FET's

Abstract: A new two-dimensional model of a GaAs FET is proposed. The model takes into account diffusion processes and Gunn-domain formation under the gate but it requires a very small computer time. The electric-field profiles under the gate, current-voltage characteristics, the dependences of the transconductance and gate-to-source capacitance on the drain voltage, and the dependences of a characteristic switching time and power-delay product on the device thickness are calculated. The results of the calculation agree well with the experimental data found earlier by other authors. The proposed model can be used for a computer-aided design of GaAs FET amplifiers and logic elements and also for a comparative study of GaAs and InP MESFET's.

Method for detection of the angular position of a part driven in rotation and instrumentation using it

Abstract: A shaft, the angular position of which is to be detected, equipped with a notched disk one tooth of which has been removed. A position sensor detects the passage of the teeth for a Schmitt trigger with its output connected to the inputs of two monostable multivibrators, to the up-down counter input of a counter, to one input of an AND gate and to the inputs of logic circuits. The held output of the counter is connected to an input of a type D flip-flop connected at its output to the second input of the AND gate.

FATRAM-A Core Efficient Cut-Set Algorithm

Abstract: Many algorithms have been developed for determining minimal cut sets for logic models (in particular, fault trees). Although these methods are theoretically correct, computer implementation of these algorithms proves them less efficient than is desirable. This paper presents a new method for determining the minimal cut sets, which makes more efficient use of computer memory. The gates are resolved in a deterministic manner according to the following rules: 1) AND gates and OR gates with gate inputs are resolved; and 2) OR gates with only basic event inputs are resolved last. Other computer techniques provide increased efficiency for implementing this method. The FATRAM algorithm for finding minimal cut sets for fault trees does use computer core memory effectively. The use of stacks (last-in first-out arrays) for the AND and OR gates has also increased the efficiency of the program. The use of dynamic storage makes the program more flexible.

Method of making implant programmable N-channel ROM

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate ROM manufacturing methods. Instead of moat programming or contact programming as is used in almost all standard processes, however, the ROM is programmed by implant after the polysilicon level of gates and interconnection has been deposited and patterned and prior to metal deposition. Address lines and gates are polysilicon, ground lines are defined by elongated N+ regions, and output lines are metal strips contacting the N+ diffused drains. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned photoresist as a mask prior to application of the polycrystalline silicon.

Modular system for obtaining pneumatic logic circuits

Abstract: The invention relates to a method and a pneumatic system which permit the definition of the logic equations of the various sequences of a machine cycle and the assembling of the various components processing said logic equations by juxtaposing them one after another along a same line with automatic setting up of certain interconnections between the components through the medium of the bases supporting said components. Furthermore the structure of said bases permit the juxtaposition on the same line of several functional components such as storage modules and logic modules.

Device for monitoring the function of electromagnets

Abstract: A first amplifier measures the instantaneous voltage across a resistor, connected in series with the electromagnet of a solenoid valve, as the current increases following energization of the electromagnet. A second amplifier measures the same voltage and stores the peak value in a capacitor. The two measured voltages are applied to a comparator which detects the difference, and generates an output, when operation of the electromagnet armature causes a transient reduction in the resistor voltage. Initial energization of the electromagnet sets a memory and starts a monostable timing period. The set output of the memory primes one input of an AND gate, the second input being inhibited by the monostable output during timing. If the electromagnet armature operates normally, the comparator output resets the memory and removes the AND gate priming signal prior to completion of the timing period. If the armature fails to operate the monostable output following the timing period completes the actuation of the AND gate to produce a fault signal.

Closely-spaced double level conductors for MOS read only

Abstract: Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

Charge transfer type semiconductor device

Abstract: PURPOSE:To readily perform digital discrimination by applying a device to the output part of a multilevel charge transfer type device and converting (l) level differences to differences of number of pulse productions. CONSTITUTION:An output gate X(21) which is driven by a clock fx, a gate Y(22) which is driven by clock phiY, a gate 23 of DC voltage application and an output diffused layer 18 are sequentially arrayed in adjacency to the final transfer electrode 3phi3. The gates 21, 22 are respectively constituted by two sheets of eletctrode of upper and lower layers and the gate 23 is constituted only by the upper layer electrode. The insulation film under the upper layer electrode 36 and gate 23 is thicker than that under the lower layer electrode 37 and even if the upper and lower layers are of the same potential, a setp difference occurs in the potential well right thereunder. The area for the charge accumulation capacity of the well under the electrode 37 is so determined that when pulse voltages phi1-3 are applied to the transfer electrodes it becomes 1/3 the storage capacity of the well with all cases. By this manner, the charge information having been dividedly filled in the wells is flowed out time serially to the output and the multilevel signals are drawn out as the time serial charge flow out signals whereby digital discrimination may be readily made.

Method of making post-metal programmable MOS read only memory

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. The ROM is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned. Address lines and gates are polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.

Method of making a metal programmable MOS read only memory device

Abstract: A metal-gate MOS read only memory or ROM array is formed by a process compatible with N-channel silicon gate manufacturing methods for circuits peripheral to the array on the same chip. The ROM is programmed at the time the metal level of contacts and interconnections, is patterned. Address lines and gates are metal in the array, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by patterning the metal to cover the gate or not. After metal patterning, the array is ion implanted through exposed gate oxide in the gates not covered by metal so that degradation is prevented.

Timing pulse generation circuit

Abstract: PURPOSE:To produce an arbitrary pulse width, delay time and pulse pattern, by outputting the pattern set to the shift register in synchronizing with the clock. CONSTITUTION:When the signal is ''1'' after the desired pattern is set in the switch by operating the dip switch 2, ''1'' is inputted to the NAND gates 61 to 64 via the AND gate 7 to open the gate and to write in desired pattern to the flip flops D1 to D4 constituting the registers. The pattern written in is shifted when the clock pulse is fed to the input terminal CE of the flip flop to output as Sout.

Semiconductor read only memory using MOS diodes

Abstract: A semiconductor integrated circuit functioning as a read only memory or ROM employs MOS diodes as the memory cells and is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Row address lines are metal strips and gates are polysilicon segments, while output or column lines are defined by elongated N+ regions. The gates are shorted to N+ drain regions to provide diode-like cells. Each MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide, rendering some cells of such high threshold that they will not turn on. Alternatively, the array may be contact programmable.

Pneumatic hopper gate

Abstract: An outlet gate arrangement for a hopper having sloping side walls converging toward each other and defining between their lower edges a discharge opening communicating with a pneumatic discharge tube comprises a gate having an upper surface abuttingly engageable with the lower edges of the side walls, a gate operating mechanism having a part movable transversely of the discharge opening, the gate being pivotally connected to the transversely movable part such that, upon movement of the transversely movable part and the gate from a closed position, a portion of the gate slidably follows the bottom surface of one of the side walls permitting the gate to pivot about its pivotal connection to the transversely movable part and thereby move the gate out of sealing engagement with the lower edge of the other side wall and away therefrom to permit discharge of lading through the discharge opening. The operating mechanism includes a manually actuated linkage for moving the transversely movable part between gate open and gate closed position.

Lsi parameter setting system

Abstract: PURPOSE:To minimize the number of the setting terminals in case the parameter is set up at the IC or SI by securing the setting or definition for more than two parameters via one unit of the parameter setting terminal CONSTITUTION:Parameter setting signals H and L plus signal 2T featuring the H and L alternating in period T are supplied through parameter setting terminal S The clock pulse of period T is applied to terminal T from clock pulse generator 2, and the parameter setting signal is latched by latch circuit 1 with the fixed period timing Input X1 and output X2 of circuit 1 are supplied to AND gate 3 and OR gate 4, and the output S1 and S2 deliver three sets of output signals H/H, L/L and H/L through terminal S based on the table and in accordance with input H, L and 2T each

Junction type field effect transistor and its production

Abstract: PURPOSE:To improve high frequency characteristics by reducing the spacing between source region and gate junction region which determine gate length and source resistivity through controlling of overetching

Keyboard control circuit

Abstract: PURPOSE: To prevent the error due to stray current between the switches when three or more switches are depressed at the same time, by providing the gate circuit which makes ineffective the signal outputted during the cycle, when the number of count is three or more. CONSTITUTION: The clock from the oscillation circuit 2 is counted at the X counter 3 and the Y counter 4, and the carry out signal is outputted when the both counters are full. This signal 20 is fed to the clear terminal of the two-bit counter 10 via the delay circuit 400, making the counter 100 to initial state. When three key switches between the carry out and the next carry out are depressed, the NAND gate 200 is conductive when the counter 100 counts the third coincidence signal 10, closing the AND gate 300 and holding it so that the signal 10 after that is not entered to the counter 100. Thus, the error due to stray current between switches when three or more switches are depressed at the same time can be prevented. COPYRIGHT: (C)1979,JPO&Japio

Monostable multiivibrator circuit

Abstract: PURPOSE:To ensure a free setting for the width of the generated rectangular wave by adjusting the electric potential at the point where one input terminal is connected via resistance in accordance with the threshold voltage of the element composing an AND gate.

INTERPOLATIVE PCM DECODER UTILIZED FOR .mu.-LAW AND A-LAW

Abstract: An interpolative PCM decoder converts PCM signals having polarity bits, segment selection bits and uniform quantization bits into an analog signal. The PCM decoder may be used both for μ-law and A-law conversion by use of simple circuits and includes an AND gate circuit which produces a logical product between a selection signal for selecting a minimum unit of an analog value of a lower end of a segment and a control signal for change-over between the μ-law and the A-law, and a circuit generating the same analog values as the minimum unit of the analog value in accordance with an output of the AND gate circuit.

Misstype semiconductor device and its manufacture

Abstract: PURPOSE:To fabricate a flat-surface MIS device with small gate-electrode wiring resistance, by burying a gate insulation film and gate electrode in the substrate and by forming a channel and gate electrode through self-matching

Smaller memory cells and logic circuits

Abstract: A method and device are disclosed for reducing the circuit size of a class of circuits including many memory cells and logic circuits. Selected drain to bulk or source to bulk transistor junctions are made leaky. The leaky junctions perform their intended (non-leaky) functions as well as the functions of certain other circuit elements. These other elements may therefore be eliminated from the circuit.

A microprocessor-compatible high-speed 8-bit DAC

Abstract: The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the converter appears as a memory location to the microprocessor. It can be programmed to operate in a wide variety of modes and can interface with the fastest MOS and TTL microprocessors. The converter offers high-speed multiplying operation and an output current mode multiplexer. Status latches are provided to store multiplexer and code select commands. Nonsaturating multilevel logic operating nearly in the linear region provides gate delays of less than 5 ns when fabricated on the same chip with precision linear functions.

Driving method of matrix type liquid-crystal display unit

Abstract: PURPOSE: To obtain an excellent contrast unit with liquid crystal long in life, by applying a voltage, which has positive and negative pulse-zero voltage periods, to a source line and by separately applying a common voltage corresponding to scanning lines of a gate line. CONSTITUTION: At intersections between several source lines 1 and several gate lines 2, thin-film transistors TFT3 are formed and liquid-crystal bodies 4 are held between striped common electrode 31 and TFTs 3, thereby obtaining a unit using bodies 4 as picture elements. In this unit, when picture element (ij) at the intersection between source line (i) and gate line (j) generates voltage VLC ij by source voltage VS i and gate voltage VG j in case of an odd frame and write operation is performed and in case of an even frame, no write operation is done since VS i is zero, but voltage VC j equal in waveform and level to VLC ij is applied reversely from common electrode 31. To cover positive and negative asymmetrical characteristics of the TFT, positive and negative pulse widths of voltage SS i are varied and when the TFT is OFF, positive and negative discharge voltages are made zero; and then, AC driving operation containing no DC component is made possible only in one direction with characteristics excellent. COPYRIGHT: (C)1979,JPO&Japio

Integrated logic circuit arrangement

Abstract: An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.

Voice data simultaneous transmission system

Abstract: PURPOSE:To make it possible to transmit simultaneously voice and data and make it possible to eliminate troubles such as economic disadvantage, deterioration of use efficiency and a large delay by inserting data to voice information as required. CONSTITUTION:The output of transmitter 11 is connected to A/D converter 12, and the output is branched and supplied to parallel-series converter 13 and selector 14. Meanwhile, the output of data terminal 15 is stored in buffer memory 17 through interface 16. Memory 17 is controlled by clock pulse generator 18 and gates 19 and 20, and FF circuit 21 is set by the output of memory 17 and is reset by timer 22. FF circuit 21 is connected to not only selector 14 and differentiating circuit 23 but also one input terminal of gate 20 through delay circuit 24. Parallel-series converter 13 and differentiating circuit 23 are connected to unipolar/bipolar converter 25, and the output of converter 25 is transmitted to the subscriber's line.

Power closing control system

Abstract: PURPOSE:To inhibit the closing, for a fixed time since power supply is cut off, by using a digital circuit such as an AND gate, FF, timer counter and decoder.

Method and apparatus for note attack and decay in an electronic musical instrument

Abstract: The present invention is a two-part apparatus for producing note attack and decay in a conventional electronic musical instrument. Either part of the invention may be used independently of the other; however, at present the combined use is preferred. In part one, there is provided an eight state counter clocked at a rate equal to the note generator cycle and a digital magnitude comparator. The inputs (A) from the eight state counter are compared to the attack and decay scale factor inputs (B) by the comparator. The A>B,A=B functions are generated by the comparator in combination with an OR gate. The OR gate output and the sample gating signal from the conventional musical instrument are applied to an AND gate which outputs a modulated sample gating signal. In part two, the modulated sample gating signal of part one is subpulsed individually by two subpulses. Through the use of gating techniques, the most significant bit of the attack and decay scale factor is used to combine the modulated sample gating signal with the first of the two subpulses. Upon reaching the maximum pulse frequency with the first subpulse, the most significant bit of the attack and decay scale factor forces the continued maximum frequency output of the first subpulse and begins a second combination using the second of the two subpulses. The second output is combined with the first through OR gating which results in a signal with both sample period and pulse width modulation.

Check number counter device for paper counting machine

Abstract: Herein disclosed is a check number counter device for use with a paper counting machine, by which sheets of paper are counted while being sucked and taken off (or deflected) one by one with the use of rotatable suction cylinder. The check number counter device includes an AND gate which is made responsive to both a coincidence signal indicating that the number checking operation is terminated and the operation terminating signal indicating that the operations of the suction cylinders are terminated so that it may generate a gate output, when it receives both the coincidence signal and the operation terminating signal, but may not generate the gate signal when it receives the latter signal but not the former signal. Further inclusive is a check number counter which is made responsive to the gate signal of the AND gate so that it may count the checked number.

Bus selection system

Abstract: PURPOSE: To ensure an easy increment and cut-off for the transfer device and also to omit the private data transfer request line by having the decision for propriety of the request continuation via the transfer device which gave the data transfer request CONSTITUTION: When the bus using right is selected, the signal is transmitted to selection line 209 to become to the input of AND gate 230 and then to set FF231 Selector 229 delivers the output of decoder 232 with excitation of gate 231 and delivers the output transfer data otherwise Encoder 233 inverts data lines 200W207, and as a result a comparison is given at comparator 234 between M and constant 7-K Then the display of M≥7-K excites gate 230 As a result, the transfer request is cancelled in the case of M<7-K and continued vice versa FF231 is set at the transfer device featuring a high priority, and FF237 is det when the output of inverter 235 is 1 Thus the data transfer becomes possible Also FF239 is set by AND gate 238 when the selection is set, and FF231 is reset to reduce the output of selector 229 COPYRIGHT: (C)1980,JPO&Japio

Pcm signal processor

Abstract: PURPOSE: To prevent the generation of an unpleasant sound based on error detection of error data, by detecting error regenerated data by using a "P" coee and "Q" code, used for error corrections, in addition to a cyclic code. CONSTITUTION: When cyclic code CRC circuit 3 detects an error block while an input signal is sequentially written in memory method 1, an ERROR signal from memory method 1 becomes "1" and DATA is cut off by AND gate circuit 4. Then, correct data are restored by error data correction circuits 9 and 6 using a "P" code and "Q" code and outputted through AND gate circuit 7. Next, when circuit 3 fails to detect the error data, signal ERROR is "0" and error detection signals of the "P" code and "Q" code are outputted as output signal from exclusive-OR gate circuits 13 and 14; and an output from OR gate circuit 10 is "1" and the output signal of circuit 6 is outputted from AND gate circuit 7. If a drop-out generated on a transmission line is extremely long, corrections are impossible and an output from correction disability detection circuit 17 becomes "1", so that interpolation signal generating circuit 12 will output an interpolation signal. COPYRIGHT: (C)1980,JPO&Japio