Showing papers on "AND gate published in 1980"

Built-in test for complex digital integrated circuits

Abstract: A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).

Simultaneous signal detector for an instantaneous frequency measurement receiver

Abstract: An apparatus for use in conjunction with an instantaneous frequency measurement (IFM) receiver, for detecting the presence of two or more RF signals, differing in frequency, between the onset of the first RF signal pulse and the completion of the frequency encoding strobe. High frequency sample and hold circuits detect the level of the video upon stabilization of the leading edge of the first received pulse. Thereafter, comparators monitor both the video and sampled levels to detect defined differences therebetween. Monitoring ceases at the termination of the frequency encode strobe. Ambiguities in the encode frequency are detected by comparator unbalances, which actuate the inputs to a logic OR gate. The output of the OR gate is connected to a logic AND gate, whose other input changes in level upon the termination of the encode strobe. The output of the AND gate latches an alarm, signalling the IFM receiver that the frequency measurement is ambiguous.

Modeling and VLSI design constraints of substrate current

Abstract: Some VLSI design constraints due to substrate current will be discussed and a simple closed form expression for short channel MOS transistor substrate current is proposed. This model is based on the physical operating principle of impact ionization, as well as the electric field dependence on drain and gate voltage. By using this model, the calculated substrate current of a transistor with L eff ≃ 1.5 µm was found to be within 10% of measured values over the operating range of interest. In addition, this model also correctly predicts parasitic bipolar breakdown phenomenon as a function of gate voltage. Because of its simplicity, the model has been easily implemented into a computer-aided circuit analysis program to simulate the actual circuit with very little increase in execution time.

Determination of the Electrode Capacitance Matrix for GaAs FET's

Abstract: In this paper, a method is presented which provides the electrode capacitance matrix for GaAs FET's The method incorporates a Green's function, valid for conductors printed on or embedded in a grounded substrate, with the moment method technique Although calculations for various geometries of printed conductors are considered, emphasis is placed on the computation of self- and mutual-capacitances for the source, gate, drain equivalent circuit of a GaAs FET As an example, the speed power characteristics of a depletion-rnode GaAs FET inverter circuit are examined, as a function of device width, pad and gate length

Non-volatile, electrically erasable and reprogrammable memory element

Abstract: The invention relates to non-volatile electrically erasable and reprogrammable memories produced by CMOS technology. According to the invention, each memory element comprises only a single p-channel transistor having a polycrystalline silicon floating gate capacitively coupled to a control electrode. The thicknesses of injection oxide and gate oxide are such that the element can be programmed by avalanche of the drain-substrate junction and erased by field emission of electrons from the floating gate towards the substrate. All the voltages required can be generated on the circuit of the memory from a battery voltage of 1.5 volts.

Semiconductor memory circuit

Abstract: A semiconductor memory circuit includes a power supply terminal; a first MOS transistor; a second MOS transistor whose source, gate and drain are respectively connected to the source, drain and gate of the first MOS transistor; first and second resistors connected between the power supply terminal and the drains of the first and second MOS transistors; a data line; a word line; and a third MOS transistor whose current path is connected between the drain of the first MOS transistor and data line, and whose gate is connected to the word line. The semiconductor memory circuit further includes a write control line whose potential is set at a high level when a readout operation is effected. The sources of the first and second MOS transistors are jointly connected to the write control line.

Schottky diode-diode field effect transistor logic

Abstract: Disclosed is a logic circuit with a plurality of AND logic elements, each including a plurality of Schottky diodes with each cathode connected to a logic input and the anodes connected in common to establish an AND output. A diode pull up FET is provided for each AND output, with the source connected to the AND output, the gate connected to the source, and the drain connected to a source of positive bias potential. An OR logic element includes a plurality of Schottky diodes with each anode connected to one of the AND outputs and the cathodes connected in common to establish an OR output, while a diode pull down FET has its drain connected to the OR output, with the gate connected to the source and the source connected to a source of negative bias potential. A level shifting diode is placed between the OR output and the pull down FET. An output FET is connected through its gate to the drain of the diode pull down FET, with the source connected to ground and the drain providing a logic output from the circuit. An output pull up FET has its source connected to the drain of the output FET, the gate connected to the source, and the drain connected to the source of positive bias potential.

Earom cell matrix and logic arrays with common memory gate

Abstract: A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.

Device for driving thermal head

Abstract: PURPOSE:To control power supplied to thermal heads irrespective of characteristics of detecting elements or a change thereof, by a device wherein a change in temperature of a head base is output as a change of electric resistance in a digital signal and this output signal is converted to drive the head with the corresponding time width. CONSTITUTION:A thermistor 1 attached to a base of a thermal head is connected to an operational amplifier 2. When output of the amplifier 2 assumes H and a start pulse from a terminal 16 assumes L, an AND gate 8 is opened by output from inverter and a latch circuit 7 is driven to latch output of a counter 5. An ROM9 includes a conversion table for generating proper outputs D0-D7 by referring outputs from the latch circuit 7 as addresses. Outputs 1Q-8Q of a latch circuit 10 are connected to switch elements 11a-11h of a switch circuit 11, respectively. Operation of each of those switch elements can vary a resistance value which determines a time constant of a monostable multivibrator 12.

Relation between incremental intrinsic capacitances and transconductances in MOS transistors

Abstract: The ratio of intrinsic substrate and gate capacitances is related to the ratio of substrate transconductance to gate transconductance for a long-channel MOS transistor in strong inversion. It is shown that under certain assumptions the two ratios are approximately equal.

Superconductive latch circuit

Abstract: This superconductive latch circuit uses superconductive switching devices and can be powered by the same phase of AC power used to power other circuits with which the latch is used. The latch is comprised of a storage loop including a superconductive switch and an inductor. It is also comprised of another superconductive switch through which an AC gate current can flow and whose state determines whether or not the AC current is delivered to the superconductive storage loop. Information is stored in the loop as the presence and absence of a circulating current of either polarity. In a variation of this latch, an output of the sense circuit which detects the state of the storage loop if fed back as a control signal to the superconductive switch in the storage loop and also as one input to an AND gate to which a SET signal is also applied. AC power is switched to the storage loop when both inputs to the AND circuit are simultaneously present. In another variation, the signal which is fed back from the sense circuit is an input to an OR gate, whose output is the control signal to the switch in the storage loop. This latch reliably holds data when the AC power diminishes to zero, and also when the AC power changes polarity.

Self-aligned MESFETs having reduced series resistance

Abstract: Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using conventional photographic techniques. The inventive MESFET device has improved high device gain as a result of the elimination of series resistance, increased circuit integration density, and improved speed capability due to the elimination of spacings between gate and drain and gate and source and the improved high device gain.

Digital time-base corrector having a wide correction range

Abstract: Disclosed is a digital time-base corrector (TBC) capable of correcting not only time-base fluctuation (jitter) but also a time-base change contained in a VTR-reproduced television video signal which experiences large changes in the horizontal scanning period during, for example, special-motion reproduction. The leading edge of a horizontal sync pulse is delayed by a variable delay means, and gate pulse is produced from the delayed leading edge and non-delayed trailing edge of the sync pulse. The delay time is controlled in response to the pulse width of the gate pulse. A burst gate pulse is produced from the trailing edge of the gate pulse. The burst gate pulse gates the video signal to extract a color burst, which is used to produce a clock pulse. The video signal is converted into a digital signal and stored in a digital memory in response to the clock pulse.

Phase synchronizing circuit for use in multi-level, multi-phase, superposition-modulated signal transmission system

Abstract: A multi-level, multi-phase, superposition-modulated signal is phase detected in a four-phase phase detector with the output from a voltage controlled oscillator (VC0). The P and Q outputs from the phase detector are supplied to a plurality of phase shifters and level discriminators to generate a plurality of digital signals corresponding to various phase positions of the received signal, and the P and Q signals are also supplied to demodulator and logic circuitry. Mutually orthogonal pairs of outputs from the level discriminators are frequency multiplied in Exclusive OR (EOR) gates, the outputs of which are selectively passed through a gate circuit in accordance with the phase position of the received signal determined by the output of the logic circuitry. A pair of mutually orthogonal demodulator outputs are also frequency multiplied by combination in a second EOR gate, and the output of the gate circuit is then frequency doubled by EOR combination with the output of the second EOR gate. This frequency-quadrupled signal is then supplied as the control voltage to the VCO.

Control of variable flow of fluid - uses feedback from electro-valve drive amplifier to provide short circuit protection

Abstract: The flow of fluid is varied by an electrovalve controlled by an electronic circuit operating in the all or nothing mode. The electronic circuit is protected against short circuiting of its output and is suitable for use in a motor vehicle fuel injection system. An electrovalve (3) winding (L) with a damping diode (D1) has one terminal connected to earth while the other is connected to an amplifier (1) output. The amplifier is driven from an AND gate (7) to which the input control signal (Ei) is applied. Feedback from the amplifier output is connected via a resistor (R2) to a second input on the gate. This resistor and a capacitor (C2) connected to both inputs on the gate acts as a differentiator to ensure that the amplifier output is high only for a brief time period when the output is short circuited.

Tone detection system

Abstract: PURPOSE:To prevent the output of the tone detecting signal due the error signal and to make easy to the circuit integration, by outputting the detection signal when the incoming of a given tone signal is present for set number within a given time by the digital processing. CONSTITUTION:The timing pulse of leading of the rectangular waves of the output signal from the reception circuit 1 is formed with the wave processing circuit 3, and this timing pulse is counted at the counter circuit 4 according to the clock from the reference clock generating circuit 5, and a given tone signal is detected by controlling the detected gate circuit 6 with the output of the circuit 4. The output side of the detecting gate circuit 6 is provided with the discrimination circuit consisting of the gate circuit 15, timer circuit 16, and counter circuit 17. Further, the AND gate 20 of the circuit 15 is controlled with the timing pulse of a given time width produced from the delay circuit 18 and the monostable multivibrator 21 provided at the circuit 16, the output of the circuit 15 is fed to the counter circuit 17, and the detection signal is outputted when the detection signal of a given number is incoming within a given time width.

Power line data transmission system

Abstract: PURPOSE:To increase the reliability, by providing a circuit selecting channels without any synchronizing noise. CONSTITUTION:Channel pulses obtained by dividing one cycle of the power supply frequency by a factor of n by from a channel pulse generator 1 is generated at output terminals T0-Tn. The number of noises of each channel is counted based on the output of a noise detector 4 and each channel pulse through counters 7-0-7-n. The content of counters is judged by a numeral comparison selector 9 and a channel with least noise number is selected, and the number of this channel is stored for a fixed time with a latch 10. At transmission, a changeover switch 3 is switched to 3B side and channel pulses picked up by a multiplexer 11 and transmission data are applied to an AND gate 12 based on the channel nember stored. The output of the AND gate 12 is applied to a data transmitter and transmitted to a power line 2.

Data processing arrangement including multiple groups of I/O devices with priority between groups and within each group

Abstract: A data processing arrangement including a microprocessor and a plurality of input/output devices arranged in groups in accordance with a predetermined priority scheme. Each input/output device is capable of initiating a service request via an interrupt line to the microprocessor as a result of which a machine cycle is initiated by the microprocessor in which control signals are produced by the microprocessor and applied to logic circuitry coupled to the groups of input/output devices. The logic circuitry operates to propagate a low voltage level at the output of the input/output device initiating the service request down through the lower priority groups and to change inputs of the lower priority input/output devices from normal high voltage levels to low voltage levels. Data is then applied by the input/output device initiating the service request to the microprocessor, following which a microprocessor reset instruction resets the device. In accordance with the present invention, once a given input/output device has been pre-conditioned for resetting, the microprocessor and logic circuitry operate to prevent a change in this condition by preventing a low voltage level established at the output of another input/output device in a higher-priority group subsequently initiating a service request from being propagated to the input of the lower-priority input/output device.

Quarter micron gate low noise GaAsFET's operable up to 30 GHz

Abstract: Quarter micron gate low noise GaAs MESFET's have been developed by delineating gate electrodes with an electron beam lithography technique and by reducing parasitic source and gate resistances. At 18GHz, a noise figure of 1.9dB with an associated gain of 7dB and a maximum available gain of 11dB were obtained at drain currents of 10mA and 30mA, respectively. At 30GHz, a noise figure of 4dB with an associated gain of 5dB and a maximum available gain of 8dB were obtained. The measured noise figures are the best values reported so far, and this work has demonstrated the feasibility of utilizing GaAs MESFET's up to millimeter-wave regions.

Character broadcast receiver

Abstract: PURPOSE:To secure the instantaneous projection of at least one character broadcast program without any queuing time, by providing the nonvolatile memory and the program designation switching circuit. CONSTITUTION:In nonvolatile memory 24, the program designating code for one specified character broadcast program is memorized in the address of the corresponding channel with every TV broadcast channel. And with operation of channel selector 17, FF16 is set and the output turns to 1. Thus the AND gate of switch circuit 25 is opened, and then the designating code of memory 24 is supplied to comparator 11. Then transfer gate 8 is opened by the coincidence signal of circuit 11, and the designating code of memory 24 is memorized in main memory 15. And the output of FF16 is 1 in circuit 3, and the selected program is projected immediately under these conditions. Here if the selection is done by character broadcast program selector 12, FF16 is reset with the output turned to 0. And the information of memory 15 is projected instantaneously on the screen. In such way, at least one character broadcast can be viewed immediately.

Transistor power amplifier overload protector - is integrable on same substrate and consists of input shunting transistor switched by AND=gate connected to output and inverted input

Abstract: The device consists of an inverter which takes in the signal input and provides the input to the power amplifier and a logic circuit. The circuit contains an anomaly detector connected to the signal input and the power amplifier output and a switched shunt across the power amplifier input. The power amplifier is an MOS transistor with input to its gate, and output from its drain with its source taken to ground. The anomaly detector consists of an inverter with a rise time greater than that of the first inverter and the power amplifier, connected to one input of an AND gate, the other gate input being connected to the drain of the power amplifier. The gate output is connected to the gate of an MOS transistor which shunts the power amplifier input, and to a latched input of an alarm circuit. The power amplifier and alarm and protection may be integrated on the same substrate.

High-frequency vertical field effect power transistor and method of making such a transistor

Abstract: When it is desired that high currents should pass in such transistors, the source electrodes (S1)(S2) cannot increase their contact surface, since in the transistors of known structure there would be a fear of a risk of short circuit with the gate electrode (g) situated in the same plane as them. According to the invention, the source (31) and gate (G) electrodes are disposed according to two superposed planes, with interposition of an insulating layer (30) of silicon oxide. The applications are especially the construction of power transistors for high frequencies.

Three state loop keyer

Abstract: A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor. When the AND gate is enabled and the output signal from the exclusive OR gate is the oscillator output signal, only one of these transistors is switched ON; and when the output of the oscillator gate is the inverted signal only the other transistor is switched ON. When the AND gate is disabled, neither transistor is switched on. For polar operation of this circuit, the opposite end of the transmission line is connected through a load resistor to voltage supply common. For neutral operation either the AND gate can be enabled and disabled or the load resistor can be connected to voltage supply positive or negative.

Colour television receiver comprising at least an integrated digital circuit for processing the composite colour signal

Abstract: 1. Television receiver comprising at least one digital integrated circuit for processing the composite color signal, - with a square-wave clock generator used as a chrominance-subcarrier oscillator and generating at least four clock signals (F1, F2, F3, F4) the first of which (F1) has four times the chrominance-subcarrier frequency, and the second to fourth of which (F2, F3, F4) have the chrominance-subcarrier frequency, the first and second clock signals (F1, F2) having a mark/space ratio of 1 : 1, - with a stage providing the digital chrominance signal (C), - with a first parallel multiplier (M1) one input signal of which is the digital chrominance signal (C), and the other input signal of which is a digital chroma control signal (SE), - with at least one buffer memory to which the digital chrominance signal (C) and the third clock signal (F3) are fed, and - with binary computing stages, such as parallel adders and parallel subtracters, characterized by the following subcircuits and features serving to effect digital amplitude control of the received chrominance-subcarrier wave, digital PAL identification and color killer action as well as digital chroma control : - the chrominance-subcarrier oscillator generates a fifth clock signal (F5) having twice the chrominance-subcarrier frequency and a mark/space ratio of 1:3 ; - the third and fourth clock signals (F3, F4) have a mark/space ratio of 1:7 and are 180 degrees out of phase with respect to each other ; - leading edges of the first, second, and fifth clock signals (F1, F2, F5), coincide, while the leading edges of the fourth clock signal (F4) lead those leading edges by the period (T) of the first clock signal (F1) ; - the output of the first parallel multiplier (M1) is connected to the inputs of a first buffer memory (PS1) and a second buffer memory (PS2) whose enable inputs are fed with the third clock signal (F3), and the fourth clock signal (F4), respectively ; - the minuend input of a first parallel subtracter (ST1) is connected to the output of the first buffer memory (PS1), and the subtrachend input of the first parallel subtracter (ST1) is connected to the output of the second buffer memory (PS2) ; - the output of the first parallel subtracter (ST1) is connected to the minuend input of a first parallel comparator (K1) and to the inputs of a third buffer memory (PS3) and a fourth buffer memory (PS4), whose enable input is fed with the fifth clock signal (F5) ; - the subtrahend input of the first parallel comparator (K1) is connected to the output of the third buffer memory (PS3), and the minuend-greater-thansubtrahend output of the first parallel comparator (K1) is connected to the enable input of the third buffer memory (PS3), whose clear input is fed with the inverted burst gating signal (~B) ; - the first input of a parallel adder (AD) is connected to the output of the third buffer memory (PS3) and the second input of the parallel adder (AD) is connected to the output of the fourth buffer memory (PS4) ; - the minuend inputs of a second parallel comparator (K2) and a third parallel comparator (K3) are connected to the output of the parallel adder (AD), while the subtrahend input of the second parallel comparator (K2) is connected to the output of a first programmable read-only memory (FS1), and the subtrahend input of the third parallel comparator (K3) is connected to the output of a second programmable read-only memory (FS2), the first and second programmable read-only memories (FS1, FS2) holding an upper reference value and a lower reference value, respectively, which determine the amplitude control ; - the minuend-greater-than-subtrahend output of the second parallel comparator (K2) is connected to the count-up enable input of a first up-down counter (Z1), and the minuend-smaller-than-subtrahend output of the third parallel comparator (K3) is connected to the count-down enable input of the first up-down counter (Z1), whose count input is fed with horizontalfrequency pulses (H), while the "up" zero-crossing output and the "down" zero-crossing output of the first up-down counter (Z1) are connected, respectively, to the up input and the down input of a second up-down counter (Z2) ; - the outputs of the second up-down counter (Z2) are connected to the first inputs of a second parallel multiplier (M2) and an electronic multiple switch (US) having its second input connected to the output of the second parallel multiplier (M2), while its control input is fed with the burst gating signal (B) ; - the digital chroma control signal (SE) is applied to the input of a fifth buffer memory (PS5), whose enable input is fed with the burst gating signal (B) ; - the second input of the second parallel multiplier (M2) is connected to the output of the fifth buffer memory (PS5) ; - the output of the multiple switch (US) is connected to the second input of the first multiplier (M1), whose enable input is fed with the first clock signal (F1) ; - the minuend-equal-to-subtrahend output and the minuend-smaller-than-subtrahend output of the first parallel subtracter (ST1) are connected to the inputs of an OR gate (OD), whose output is connected via an inverter (IV) to the first input of a first AND gate (U1) and directly to the first input of a second AND gate (U2), the second inputs of which AND gates (U1, U2) are fed with the fourth clock signal (F4) ; - the outputs of the first AND gate (U1) and the second AND gate (U2) are connected, respectively, to the up input and the down input of a third up-down counter (Z3), whose "up" and "down" zero-crossing outputs are connected, respectively, to the R input and the S input of a first RS flip-flop (FF1) ; - a few, preferably three, most significant bits of the output signal of the second up-down counter (Z2) are applied to the inputs of a NAND gate (NG), and - a few, preferably five, most significant bits of the output signal of the first parallel multiplier (M1) are applied to the inputs of a multiple-input AND gate (VU), whose other inputs are connected to the output of the NAND gate (NG) and to the Q output of the first RS flip-flop (FF1), and whose output provides the controlled digital chrominance signal (CG).

Picture display device

Abstract: PURPOSE:To obtain an easy-to-see picture display by giving relative 1/2-bit shift to the signal of one field to the picture signal of the oblique lines. CONSTITUTION:The picture signals equivalent to one field are stored in memory device 1, and the same picture signal is read out twice to one frame from device 1. At the same time, the gate signals to select fields I and II are supplied to terminals T1 and T2, and the output of dealy circuit 5a and OR gate 9 are delivered alternately. In other words, in the case of field I the output is delivered to terminal T0 via the route of 1H-delay circuit 2, shift register 3a and 1-bit delay circuit 5a each; while in the case of field II the route includes circuit 2 and register 3 but thereafter is branched off into three different lines according to the operations logic arithmetic circuit 4 plus AND gates 8a1-8a3 as well as based on the state of each bit of shift registers 3a and 3b, and thus the output is delivered through terminal TD with difference of -1/2-bit, 0-bit and +1/2-bit each in comparison with the delay time of field I.

Printing sheet supply system in cash register

Abstract: PURPOSE:To achieve the feed in the number of lines set by the number setting key by memorizing a predetermined number of lines in advance in a particular memory device by the operation of the number setting key. CONSTITUTION:In the case of free supply, in RAM the open flag memory 137 is prepared. The feed open key 22 for changing-over the present memory is disposed at the key input portion. In the passage for transmitting the feed signal to the print data processing circuit 16, OR circuit 104 is provided and gives the signal from the oscillator 21 through AND circuit 139. To the circuit 139, the gate signal is given from Q output end of the memory 137 through AND gate 138. The gate signal of the circuit 138 is given from the feed flag memory 133. The memory 137 when the key operation is not done is reset to give the signal outputted from Q output end to the AND circuits 104, 106 as the gate signal. After the operation of the open key 4a, step S7 is moved to S6, and during the operation of the feed key, the continuous printing sheet delivery operation is carried out.

Lock-up type automatic speed change gear

Abstract: PURPOSE:To prevent any idle blow and speed change shock in an engine in such a way that lock-up interrupting time is made consistent with the actual speed change operating time through such arrangement as assigning individually different speed change signal output time to each speed change detecting circuit. CONSTITUTION:Input of signals out of a 1-2 shift switch 60 is given to a two to one speed change detecting circuit 207 and a one to two speed change detecting circuit 208, and input of signals out of a 2-3 shift switch 61 is given to a three to two speed change detecting circuit 218 and to a two to three speed change detecting circuit 219. Besides, output from each speed change detecting circuit is given as input through a NOR gate 217 to an AND gate 228, and further an AND gate 228 is given lock-up permission signals SL as input which is transmitted in response to the operating condition. In addition, since each time constant of the RC circuit in each speed change detecting circuit is individually adjusted, it is set so as to vary the lock-up interrupting time in response to each speed change.

Memory unit of electronic computer

Abstract: PURPOSE:To reduce the capacity of memory unit and to decrease the processing time, by converting the designated bit from one word read out into the designated logic and performing output with the logic as it is read out for other bits. CONSTITUTION:To the instruction of one time outputted from CPU to the memory unit 1, the one word designated is read out from the unit 1. Further, the conversion circuit consisting of the selection circuit 2, exclusive OR gate 3, decode circuit 4, and gate circuit 5, converts the designated bit in one word read out into designated ligic. Other bits are outputted with the logic as they are read out, and the output is written in the logic 1. Thus, the write-in instruction of one time can oparate an arbitrary one bit, allowing to reduce the capacity of the unit 1 and to decrease the processing time.

Ignition diagnosing equipment for internal combustion engine

Abstract: PURPOSE:To properly detect leak or missparks as well as normal operation in the ignition system in such a way that a discharge voltage detector and a discharge current detector are installed on the secondary side of an ignition coil, and these output signals are given as input to a diagnosing circuit. CONSTITUTION:Signal (c') from a voltage detector 11 on the secondary side of an ignition coil 1, signal (e') from a discharge current detector 12 of an ignition plug 5, signal (g) which is generated when a magnet 10 of a rotor 3r meets a lead switch 9, and signal (a) which is generated at the connecting part of the primary side 1P of the ignition coil 1 to an igniter 2 are respectively given as input to a diagnosing circuit 13. Thus, in case where the signal (c') is not detected while an AND gate 410 is kept opened by signal (n) from a counter 330, high level of signal is given as output for the purpose of mis-spark signal coming from output (p) of the gate 410. Beside, in the event that while the gate 420 is kept opened, the signal (c') is detected and signal from the discharge current detector 12 is not detected, high level of signal is given as output for the purpose of leak signal coming from the output (q) of the gate 420.

Information control system

Abstract: PURPOSE:To output high-reliability data by detecting the coincidence of received data with a noise n times continuously without outputting the data immediately, by outputting the data to an output register only when information coindides n times continuously, and by making the contents of the register remain unchanged in case of dissidence. CONSTITUTION:The unit which outputs data information inputted in series is provided with shift register 1 stored temporarily with input information, AND gate 3 and EX-OR gate 4 which output the stored input data information n times continuously according to clocks and detect the conicidence of the information outputted n times, and the logic circuit composed of OR gate 5 and AND gate 6. Further, output register 2 is provided which is stored with input data information on the basis of the output of the logic circuit, and only when input data information agrees n times continuously, the information is outputted with the contents of register 2 modified.