Showing papers on "AND gate published in 1981"

Data sense apparatus for use in multi-threshold read only memory

Abstract: A read only memory in which the memory cells are single metal gate or silicon gate field effect transistors. Each FET has one of several different thresholds or states. The size or area of the FET gates at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instant. The output of a cell is fed to several flip-flops, which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128K on a single chip. In another embodiment the input to the gates is a step, and the cells are all rendered conducting simultaneously. The amount of current drawn by each gate however, depends upon the doping in the gate region. The amplitude of the current being drawn by a selected cell is compared with the reference , this in turn is decoded to indicate the state of that cell.

Control systems for gates and the like including a motor overload monitoring circuit

Abstract: A control system for operating a bidirectional gate driven by a reversible electric motor includes an overload protection circuit to prevent motor current overload produced by gate obstructions and the like. The system includes control switches for operating gate opening and gate closing circuits which respectively energize the motor for rotation in opposite directions. The safety circuit includes a motor current sensing device and a first comparator which compares the level of sensed motor current with a temperature adjusted, selectable reference value and delivers a motor disabling signal to the opening and closing circuits if the sensed value exceeds the reference level. The safety circuit also includes a second comparator which compares the sensed current level with another reference value to produce the disabling signal in the event that the selected reference value of the first comparator is incorrect.

Storage cell for nonvolatile electrically alterable memory

Abstract: A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.

Self-aligned gate method for making MESFET semiconductor

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Digital circuits and microprocessors

Abstract: From the Publisher: This is a pedagogically conceived text in that it enables students to study in one semester what usually takes two,thus teaching every engineer or computer scientist what he or she needs to know about logic design in half a semester. For courses in logic design and microprocessors,digital logic and computer design,and switching theory and logic design.

Functional verification in an interactive symbolic ic design environment

Abstract: This paper describes verification techniques that have been implemented as part of an interactive symbolic IC design system. Circuit analysis programs perform node extraction and gate decomposition. They generate both transistor and gate level circuit desriptions which are used as input to a transistor level digital MOS timing simulator. The extraction programs make use of an intermediate circuit description language which captures both geometric placement and circuit connectivity. All programs are written in the C programming language and run under the UNIX operating system. An example is included to demonstrate the operation of these various techniques.

Phase lock loss detector

Abstract: A system for detecting phase lock loss between first and second two level signals S N and S R , and comprising an Exclusive OR (XOR) gate having first and second input terminals and an output terminal, logic for supplying S N and S R to the first and second inputs of the XOR gate so that the center points of the respective upper and lower levels are aligned and with the time intervals between adjacent leading and trailing edges of S N and S R being nominally equal to Δt. Also provided is an AND gate having first and second input terminals and an output terminal, and delay logic for supplying the output signal of the XOR gate to the two input terminals of the AND gate with such output signal arriving at one of the input terminals of the AND gate a time interval Δt after the arrival of the output signal at the other input terminal of the AND gate and a detector for detecting an output signal from the AND gate to indicate loss of phase lock.

Multiple flash adaptor

Abstract: An adaptor for a camera for operating multiple flash units with a single camera device in which all of the flash units simultaneously emit light. Output signals from each of the flash units indicating that the corresponding individual flash unit is ready to emit light are coupled to corresponding inputs of a logical product circuit such as an AND gate. The single output of the AND gate is coupled to a single corresponding input of the camera device. The X contact of the camera device is coupled in common to the actuation terminals of each of the flash units.

Car height adjusting unit

Abstract: PURPOSE:To allow a driver to take the most suitable action quickly by detecting an irregularity when it occurs so as to indicate the occurrence of the irregularity. CONSTITUTION:When a car height raising control or a car height lowering control is performed, the output of an NOR gate NOR2 is turned to (H) and the output of an OR gate OR4 is truned to (H), then a transistor Tr3 is turned on and a lamp LP is lighted. If at least one of irregularity detection circuits detects an irregularity, the output of an OR gate OR1 is turned to (H) and an AND gate AND6 is opened, then frequency divided clock pulses from a clock generator are applied to the base of the transistor Tr3 through the AND gate AND6 and OR gate OR4. Therefore, the transistor Tr3 is turned on and off, thus indicating the occurrence of an irregularity.

Sorting circuit for three or more inputs

Abstract: A sorting circuit for sorting three inputs representative of numerical values into first through third outputs representative of the values in the ascending order, checks three binary bits of input sequences supplied thereto at a time from the most significant bit. When only one of the three checked bits is found to be logic "0" and logic "1" for the first time, the sequence including the only one bit represents the minimum and the maximum, respectively. As soon as only one of two bits of the sequences except for the sequence representative of the minimum is subsequently found to be logic "1," the sequence including the only one subsequently found bit represents the maximum. In this manner, the circuit produces the outputs. It is possible to form an array of such three-input-output sorting circuits and conventional two-input-output sorting circuits for use in sorting a multiplicity of inputs. A similar array can be formed for inputs, an integral multiple of four in number, by four-input-output sorting units, each supplied with two sets of ascendingly ordered inputs. The inputs are supplied to the array through a plurality of two-input-output sorting units. The last-mentioned sorting circuit can be formed to be operable either in bit series or in bit parallel.

Syndrome-Testability Can be Achieved by Circuit Modification

Abstract: In [1] and [2] Savir developed many facets of syndrome-testing (checking the number of minterms realized by a circuit against the number realized by a fault-free version of that circuit) and presented evidence showing that syndrome-testing can be used in many practical circuits to detect all single faults In some cases, where syndrome-testing did not detect all single stuck-at-faults, Savir showed that by the addition of a small number of additional "control" inputs and gates one would get a function which is syndrome-testable for all single stuck-at faults, and yet which realizes the original function when the "control" inputs are fed appropriate values However, he left open the question of whether one could always modify a circuit to achieve syndrome-testability In this correspondence we show that a combinatorial circuit can always be modified to produce a single-fault, syndrome-testable circuit

Insulated gate field effect transistor provided with a protective device for a gate insulating film

Abstract: An improved protective device for the gate insulation of an integrated-gate field effect transistor (IGFET) is disclosed that does not breakdown under spike-like input voltages. The protective device is formed on the same semiconductor chip as an operative IGFET and includes a resistor connected between the input terminal and the operative IGFET's gate, a protective IGFET whose drain and gate are both connected to the operative IGFET's gate, and another resistor connected between the protective IGFET's source and a constant voltage source.

Memory control system

Abstract: PURPOSE:To obtain a normal data even though an error exists in both words of a doubled memory, by dividing each word within two memories into plural subgroups and then giving a check to the data with every subgroup. CONSTITUTION:No error exists at the byte position i (i=0-3) of a temporary register 3, and an error exists at the byte position i of a register 3'. In such case, a gate Gi opens by the data effective signal Si sent from a parity check circuit PCi, and a gate G'i is closed since the signal S'i of a parity check circuit PC'i is off. As a result, the output of Gi, i.e., a normal data is set at the byte position i of a reading register 5. In this case, the error detection signal ei of the circuit PCi is off. Thus an AND gate Gei is closed to deliver no error signal E to the system. The system has no breakdown as long as the position of the faulty subgroup differs and even though a fault exists in both doubled memories.

Pulse detection circuit

Abstract: A pulse detection circuit, for detecting pulses contained in output signals derived from an encoder such as rotary encoder which converts any physical quantity like spatial position, displacement or length into an electric signal, is disclosed. The disclosed pulse detection circuit can minimize the positional error in counting pulses and effectively prevent the accumulation of the erroneous count value by an ingeneous establishment and control of the logical relationship among signals by the use of a gate circuit including a plurality of AND gates and an RS flip-flop. It therefore will not erroneously count pulses contained in the encoder output signals even if noise or pulse chatter are incidentally included in the encoder output signals and if the phase relation between the two signals is temporarily inverted, to perform a pulse detection in a very high accuracy.

Implant programmable metal gate MOS read only memory

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.

Readdin method for color picture

Abstract: PURPOSE:To eliminate the level difference among color read-in signals, by adjusting the picture projection storage time of a solidstate image sensor for every color filter and further adjusting the read-in signal level for every color filter. CONSTITUTION:A clock control circuit 10b adjusts the storage time for a CCD element 6. Further, one set of operational amplifier 8 only is inserted between a preamplifier 7 and a binary circuit 9. The output of the circuit 9 is transmitted on three parallel lines depending on chroma signal at AND gates AN1-AN3, and each of the gates AN1-AN3 is ON-controlled with the respective output of AN7-AN9. The gate AN1 outputs only the readout binary signal immediately after the storage time of tR, the gate AN2 outputs that immediately after the storage time in tG, and the gate AN3 outputs that in tB.

High-tolerance three-Josephson-junction curent-injection logic devices (HTCID)

Abstract: A new 3-Josephson-junction interferometer is presented as a high-tolerance nonlinear current-injection 2-input AND gate. In Josephson LSI circuits, the tolerances are an important issue. Thus, in our new logic device emphasis has been placed on its static and dynamic tolerance properties. The new HTCID offers considerably better input-signal tolerances than known 2-junction current-injection devices (CID) for identical fabrication tolerance assumptions. The HTCID in this example has a Josephson current ratio of 1:3:1 and a characteristic phase λ = 0.72π. Including circuit parameter variations, this new 3-junction CID allows attractive, high input-signal tolerances of ± 33.3%. Therefore, an almost threefold tolerance improvement over the published 2-junction CID (λ = 0.66π) could be achieved. Trade-off between signal tolerances and device speed is discussed. Computer simulation indicates a worst-case delay of less than 47 ps.

Arrangement for the digital measuring of phase difference

Abstract: For the digital phase difference measurement between a particular transmitted and received, refer-. Renz pulse sequence (RF) and a pulse train (F) as an output of a frequency divider (FT) for a clock signal (TF) is formed whose frequency is at least an order of magnitude higher than that of the pulse train (IF), are the three inputs of a first AND -Glieds (UG1), the clock signal (TF) and the reference pulse train (RF) or a from the frequency divider (FT) derived switching signal (SF) supplied to the twice the frequency of the reference pulse train (RF) and a pulse-pause ratio of 1: 1 nat. The three inputs of a second AND gate (UG2), the clock signal (TF) and the reference pulse train (RF) and the inverted by the frequency divider (FT) derived switching signal (SF) are supplied. The outputs of the two AND elements (UG1, UG2) each lie at the counting input of a first and a second forward counter (Z1, Z2) and its outputs to the inputs of a subtracter (SS1), at whose output the phase difference digital signal (PhD) occurs. Thereby an accurate measurement is also possible when in the reference pulse train (IF) statistically distributed interference / noise pulses occur, and the measuring range is not limited by them. When used for synchronizing the pulse train (IF) with the reference pulse train (RF), wherein the frequency divider (FT) is an adjustable frequency divider (RTD), and its division ratio in dependence upon the averaged over an averaging time phase difference (PhD) is set, and the averaging time equal to a greater number of periods of the reference pulse train (IF) is, the variable frequency divider (RTD) is an m-stage (m = integer) binary divider, and the number of periods is equal to a n-th power of two (n integer and at least equal to five). The beginning and the measured at the end of the averaging time both instantaneous phase difference digital signals are a subtracter (SS2) supplied to the output via a first n-stage binary divider (BT1) at one input of a first adder (A1). The phase difference digital signal (PhD) is located at an input of a second adder (A2) whose output signal is fed to a first memory (SP1), and whose output is connected to the other input of the first adder (A1) and connected to one inputs of a first connected coincidence gate (KG1) whose other inputs to the counter reading outputs of the adjustable frequency divider (RTD) and the output at the reset input of the variable frequency divider (RTD) is located. The first inputs of a second coincidence gate (KG2) is in the first memory (SP1) binary word given without its least significant digit, and whose other inputs the outputs of the variable frequency divider (RTD) are fed while the output at the S input and the output of the last frequency divider stage to the R input of a RS flip-flop (FF) is, at the Q- or Q-output of the switching signal (SF) and the inverted switching signal (SF) is formed. The takeover input of the first memory (SP1) is connected via a first delay stage (VS1) to the C output of the RS flip-flop (FF), and the output of the first forward counter (Z1) is greater than a second memory (SP2) of the subtractor circuit is connected (SS1), to the upper takeover input of the Q output of the RS flip-flop (FF) with the interposition of a second delay stage (VS2). Instead of the first and second forward counter (Z1, Z2), a single up-down counter may be provided which counts alternately during each one period of the pulse train (IF) in forward and reverse directions.

Magnetic disc device

Abstract: PURPOSE:To make the recording density of a disc constant, by switching a reference oscillating frequency reading a writing frequency at each block or switching the rotational number of a floppy disc. CONSTITUTION:The 1st block oscillator 2 oscillates a frequency corresponding to the rotational number of the 1st block, oscillators 3 and 4 oscillate frequencies corresponding to the 2nd and the n-th block respectively. The 1st block signal (a) is connected to an AND gate 5 with the 1st oscillation signal (d), the 2nd block signal (b) is to an AND gate 6 with the 2nd oscillation signal (e), and the n-th block signal (c) is connected to an AND gate 7 with the n-th oscillation signal 5. An output of each AND gate is connected to an OR gate 8 and a reference oscillation signal (g) is connected to a phase comparator 9 being a part of the rotational number controlling circuit of a motor rotating a floppy disc 7. A tachogenerator pulse (h) being the motor output is connected to another input of the phase comparator 9.

Rewritable Programmable Logic Array of Current Mode Logic

Abstract: This paper describes new ways to construct a rewritable programmable logic array (R-PLA) of current mode logic (CML) and to control READ/WRITE operations of the R-PLA. The R-PLA is constructed by splitting a conventional Random Access Memory (RAM) of CML into two parts. Therefore, each cell structure of the new R-PLA is identified with that of the conventional RAM, differing from a complicated cell structure proposed in the past. Because of the identification the comparison for the number of cells between the new R-PLA and the RAM becomes possible according to the historical discussions of the PLA and the memory. It will be demonstrated logically and electrically that SEARCH and READ parts of the new R-PLA can perform logic-in-memory without using special AND gates in each cell in the READ mode and can enter a WRITE data from a word direction in the WRITE mode.

Automatically stopping and restarting device of engine

Abstract: PURPOSE: To ensure safety, by generating an alarm when a vehicle, with an engine at an automatic stop state, begins to move at the necessity for a vehicle brake and increase a car speed to at least a prescribed value further with booster pressure of the brake in a prescribed value or less. CONSTITUTION: A car speed sensor 12, detecting a vehicle run-stop condition, negative pressure switch 13, detecting booster pressure of a brake, and an ignition circuit 14 are connected to a control circuit 1, having AND gates 90, 100, while informing unit 80, equipped with an alarm lamp L 1 and buzzer Bz, is connected to said control circuit 1. For a car speed at least a prescribed value further with the booster pressure in a prescribed value or less, a logical signal "1" is output from the AND gate 90 to turn on the alarm lamp L 1 , simultaneously the buzzer Bz is sounded to generate an alarm to the driver. Further the logical signal "1" of the AND gate 90, ignition signal from the ignition circuit 14 and a decision signal 110 are input to the AND gate 100 to output a logical signal "1", and a neutral switch 43 is closed to start an engine, then safety at the necessity of a vehicle brake can be ensured. COPYRIGHT: (C)1983,JPO&Japio

Switching device for detecting interruptions in transmission lines

Abstract: In a transmission system employing a plurality of parallel lines for transmitting serial digital signals, means are provided in each line for detecting and disconnecting any line on which transmission is interrupted comprising a converter for producing two signals of opposite polarity, a receiver for reconverting the signals connected to the converter by a pair of transmission lines, an exclusive OR gate connected to the pair of transmission lines for providing an output when normal signals of opposite polarity are present, and a switch comprising an AND gate converted to the receiver and to the exclusive OR gate which disconnects the receiver when no output is received from the exclusive OR gate. The received signals from each line are combined through a common OR gate.

Semiconductor storage device

Abstract: PURPOSE:To prevent the output of erroneous readout information by invalidating readout information from a storage cell through detecting short-circuit defection, etc., between an address buffer and decoder. CONSTITUTION:Addresses Cq and Cq' from address buffer 1 are applied to exclusive NOR circuit Pq of detecting circuit 7, whose output is applied to the set terminal of RST type FF via OR circuit 9. Consequently, the set output of FF12 is inverted to the high level because addresses Cq and Cq' are the same signal if output line Bq between buffer 1 and decoder 2 is short-circuited or almost short-circuited, so that output-side AND gate 13 of information invalidating circuit 8 will be released via inverter 14. Therefore, the output of erroneous readout information from multiplexer 4 of storage cell storage circuit 3 is prevented. Further, the same effection is obtained by inhibiting the application of an erroneous address due to a short circuit to the decoder.

Internal combustion engine ignition system test apparatus

Abstract: To permit tests of: ignition timing; dwell angle; engine speed; and voltage levels, a pulse train is provided derived from the ignition system of the engine; the pulse train is applied to a frequency multiplier, preferably a phase locked loop (PLL) which provides a sequence of output pulses having a pulse repetition rate which is a multiple of the frequency of the signals or pulses of the pulse train. An AND gate has the multiplied signals applied thereto and is enabled, selectively, in accordance with the desired test. The output of the AND gate is applied to a counter which counts multiplied pulses within the interval of enabling of the AND gate, the output being applied to a digital indicator to provide a direct readable digital output; preferably, the multiplication rate is selected to provide a digital output indication which is directly readable in desired units. To determine dwell angle, enabling pulses are applied to the AND gate from the ignition system; to determine spark timing, derived enabling pulses are applied to the AND gate, derived from the ignition system upon being compared with a reference signal, for example an upper dead center (TDC) signal; to determine speed, the enabling pulses are applied with respect to a clock reference; and to determine a voltage test level, the input to the system is disconnected and the test voltage applied to a voltage controlled oscillator of the PLL.

Bold printing system

Abstract: PURPOSE:To realize a bold printing easily by adding a simple circuit without providing a special circuit or mechanism, by making a part of bit forming a character have the mechanism detecting whether the bold printing exists or not CONSTITUTION:When a printing data PRTDET is transferred from CPU, etc, it is stored in the buffer memory, etc once, it is output in order through the data buses 10-12, and an alphanumeric code is input to the character discriminating circuit 1 This code is decoded by this circuit 1, and logic 1 is output to the A/N character line, the space line and the line corresponding to other character And in case of bold printing, the sequential circuit of the 1 character printing control circuit 3 is operated by a data of the bolt bit line 12, and a strobe signal is output In this way, the AND gate 7 is closed, the AND gate 6 is opened, the code such as an A/N character or a symbol, etc through the data bus 10 from the buffer memory, etc is made a data, and it is input to the printer interface circuit 4

Four input coincidence detector

Abstract: A gamma ray scintillation coincidence detection circuit having four inputs connected to two gating configurations, fed by gamma ray detector units. Detection in any one of the four inputs develops a disabling signal in one signal path leading to an AND gate. Detection in any two of the four inputs results in a system output in another signal path. When any input goes high, the AND gate is disabled after a predetermined settable time delay T. If a second input goes high before the expiration of the delay time T, then the signal in the other path can pass through the AND gate and sets a latch, signifying that detector coincidence has occurred.

Buffer memory circuit

Abstract: PURPOSE:To easily constitute a circuit by use of an FIFO memory IC on the market, by detecting an abnormal if it should occur in the frame format of an output of an output of the FIFO memory, and making automatically recover it to its normal state. CONSTITUTION:When an abnormal has occurred in the output of the FIFO memory 32, the output 309 of the marker detection circuit 33 becomes ''0'', the output 310 of the NAND gate 372 becomes ''0'', and the memory 32, the FF's 34, 35 and the counter 36 are reset. As a result, the contents of the memory 32 are cleared, and also write and read are stopped. After that, when the write frame position designation pulse 306 becomes ''0'', the FF34 is set and inhibition of the AND gate 371 is released, therefore write of a data is restarted. When a clock is applied to the clock input CK of the counter 36 after restarting, the counter 36 starts to step, and when it has reached the prescribed counting value, the carry output 315 becomes ''1''. After that, when the read frame position designation pulse 307 is applied to the FF35, the output of the FF35 becomes ''1'', therefore read of the memory 32 is restarted.

Control system reducing fuel consumption IC engine - uses AND=gate as aid to driver in selecting best speed for given loading

Abstract: The control system has a speed-dependent and a load-dependent switch (6,8) acting as AND-gate in the drive circuit (2) of a signal generator (4). These two switches only close the drive circuit when the engine is operating at points lying within a given area of a power/speed diagram. This given area is remote from the region of full loading. The AND-gate also contains a switch (10) dependent on gear and disconnecting the drive circuit only when the highest gear has been selected. The given area lies above a given speed of c. 20-50 per cent of the max. speed and below a line describing c. 50-70 per cent of the max. position of the power setting device.

Fuel feeder for car mounting automatic speed change gear

Abstract: PURPOSE:To reduce the speed changing shock when performing the shift up, by lowering the fuel pressure during the shift-up to reduce the fuel supply thereby reducing the engine output and suppressing the peak torque low. CONSTITUTION:Upon the shift-up of an automatic speed change gear from second speed to third speed, 2-3 shift switch 19 is turned off while the signal from the switch 19 is provided to an inverter 26a and an AND gate 26b to produce a H level signal. It is provided to a NOR gate 25b then a H level signal produced at the gate C' of the NOR gate 25b is lagged by time T1 through a delay circuit 26 and outputted, to lower the fuel pressure and to suppress the peak torque even when performing the shift-up of the fuel pressure lowering time to third speed. Consequently the speed change shock can be reduced.

Submicron gate MOSFET's with channel-doped separate gate structures (SG-MOSFET's)

Abstract: Submicron gate MOSFET's with a new device structure are presented. The device features gate separation between the source and gate and between the gate and drain. The minimum gate length limited by V TH lowering is extended into the submicron range. Experimental results showed pentode-like current-voltage characteristics without punchthtough, even in the submicron range. Experimental results of inverter circuits and theoretical analysis predict high-speed operation in the subnanosecond region.