Showing papers on "AND gate published in 1982"

GaAs LSI-directed MESFET's with self-aligned implantation for n + -layer technology (SAINT)

Abstract: Self-aligned implantation for n+-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n+-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-law I - V fitting has been improved by a factor of 3.4, compared to conventional FET's without the n+-layer. Thermal emission for carriers from the source n+-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.

Correlation between substrate and gate currents in MOSFET's

Abstract: A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.

Self-aligned transistor with sidewall base electrode

Abstract: A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 1\4 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.

Solid-state image pickup device

Abstract: PURPOSE:To perform high speed operation, by using a junction type FET switch controlled with an address signal applied between the gate and the drain, and reading a current of a photo diode or a photo transistor CONSTITUTION:The unit consists of a photo diode consisting of a substrate 8 and a semiconductor layer 9, a junction type FET switch taking semiconductor layers 9 and 10 as the source and the drain and taking the substrate 8 as the gate, a source 11 driving the switch, an AND logical switch for X-Y address comprising a drain 12, and gates 13 and 8, and the unit switches picture elements A positive voltage is applied to the substrate 8 from a power supply 16 and a photoelectric charge is stored to the junction between the semiconductor layer 9 and the substrate 7 A voltage between the gate 8 and the drain 10 conducts between the gate 8 and the drain 10, to reset the charge of the photo diode and a reset current flowing at this time is read to form a photoelectric conversion signal

Adaptable value token

Abstract: A portable on-person data component comprising in a unified construction a highly integrated circuit capable of performing data logic and processing fucntions, is connected, on the one hand, to means (1) arranged on the component for manually inserting command data into keyboard scanning and logic recognition circuit (2) representing for example program data or a personal identity number, on the other hand is also connected to input/output circuitry (15) which is accessible from the outside solely via a reactive coupling link (capacitive or inductive coupling). The device includes a long-life battery for maintaining the various memory circuits. Clock pulses received via an inductive pickup loop (20) partially recharge the battery during every use cycle, and provide the basic synchronization with the circuitry in the terminal to which the component is coupled. There is also a display device (13) on which the holder may call up any of a number of data records held in data stores (5 and 6). Other stores in the circuitry cannot be read out nor displayed, such as for example the instruction registre or the personal identity register preset in the component. it is a feature of the invention that program data can be introduced via the reactive interface (17) in order that the processing steps may reflect the nature of the terminal into which the component is inserted and interfaced by proximity. It is clear that different performance tasks are to be performed when the terminal is: a vending machine, an electronic game input device, a bus farebox, a train access gate, a security access gate, etc. Program Data entered into a data component by a terminal are arranged to cancel any incompatible program data entered manually via the keyboard (1).

Resistor coupled Josephson logic

Abstract: A resistor coupled Josephson logic (RCJL) family, composed of OR, AND, and 2/3 majority gates, is proposed. The RCJL family consists of multiple Josephson junctions and resistors, and employs current injected switching. OR gates have I‐O isolation capability with high input sensitivity and wide operating current margin. In the AND gate, current margin as wide as the CIL AND gate and higher input sensitivity can be achieved without inductors. Experimental verification of the RCJL family operation is also described.

Front gate and latch assembly for the guide body of an industrial fastener driving tool

Abstract: A front gate and gate latch assembly for the guide body of an industrial fastener driving tool of the type wherein the guide body and front gate, in closed position, define a drive track for the tool driver and fasteners. The gate is pivotally affixed to the guide body and is swingable between a closed position against the guide body and an open position. A latch plate having tapered end portions is slidably and captively mounted on the gate. A spaced pair of locking blocks are mounted on the guide body to either side of the gate. The latch plate is shiftable along the gate between a gate locking position wherein the latch plate ends are in wedged engagement with the locking blocks and a gate release position free of the locking blocks. The latch plate is shiftable by a manually actuable over-center locking lever assembly.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce the capacitance of the gate of the semiconductor device, and to stabilize electrical characteristics by preventing the stacking of a source-drain impurity to the gate and self-aligning the gate and a drain. CONSTITUTION:A gate oxide film 5 is formed, poly Si is shaped onto the whole surface, the N type impurity is diffused and a conductor is formed, and gate metals 4, 4' are shaped lest source regions 11a, 12b and drain regions 11b, 12a should be stacked. Resists 13 are left, and a PMOS transistor region is masked, and impurity regions 14a, 14b with the same conduction type as the source region 12b and the drain region 12a are molded through ion implantation. The positions of the source region 12b, the drain region 12a and the gate metal 4' are determined in a self-alignment manner at the time. Impurity regions 17a, 17b with the same conduction type as the regions 11a, 11b are shaped into an NMOS transistor region through a mask-ion implantation method. Since the quantity of the impurity dosed for shaping the impurity regions 17a, 17b, 14a, 14b is little, the impurity does not penetrate the gate, and VTH does not change.

Measuring energy consumption in VLSI circuits: A foundation

Abstract: Energy conservation is a key question in today' s society and the proliferation of VLSI circuits encourages an energy conscious approach to their design. Although a single chip at current densities may consume less than one watt of power, assembling larger and larger systems with these chips results in significant energy costs [Me 80]. Moreover, energy consumed by a circuit is dissipated, typically by convection, as heat. The heat dissipated is proportional to the energy consumed. Increased densities in planar technologies and the possibility of 3-dimensional technologies, therefore, increase the need to reduce the amount of heal. produced. The intent of this paper is to lay the ground work for measuring the switching energy consumed in VLSI circuits. Intuitively, switching energy measures the area “used” to effect a computation. A wire or gate consumes switching energy when it changes staie from 0 to 1 or from 1 to 0. Some technologies consume more than switching energy. For example, nMOS dissipates DC power [MC 80]. CMOS, however, consumes only switching energy [MC 80]. Switching energy is thus a lower bound on total energy, and is alternately termed “energy” throughout this paper. In this paper, two energy models are developed, Model 1, the Uniswitch Model (USM), assumes that a wire or gate in an acyclic circuit can switch at most once. In particular, wire delays are neglected, the affects of different path lengths are neglected (ie. circuits are synchronous [Sa 76]), and all inputs are assumed to arrive together. Model 2, the Multiswitch Model (MSM), is more sensitive to timing issues that can cause wires and gates in an acyclic circuit to switch more than once. The rest of this paper is organized as follows. Section 2 defines the energy models. In section 3, a class of restricted acyclic circuits is defined. Lower and upper bounds for worst case energy are obtained for these circuits. An Ω(area) lower bound is obtained for acyclic monotone circuits. In section 4, average energy bounds are obtained for the restricted circuits.

Stem connection for gate valve

Abstract: A reciprocating gate valve having an adjustable low stress stem connection structure (70) for connecting an operating stem (42) to a gate member (24). The connection structure includes a stem extension (78) formed on the bottom end of the operating stem (42) threadably receiving a collar (84) having an axial bore (86) coaxial with the stem (42) and extending therethrough receiving a gate extension (72) formed on the top end of the gate member (24). The collar (84) has a slot (96) extending generally perpendicular to the axial bore (86) in the direction of fluid flow through the valve. An adjusting nut (106) fits into the slot (96) and threadably engages the gate extension (72). The slot (96) permits movement of the nut (106) and gate member (24) relative to the longitudinal axis of the stem (42) in a direction generally parallel to the direction of fluid flow through to the gate valve. The nut (106) is accessible from the slot (96) for manual axial adjustment of the gate member (24) relative to the stem (42) so that the gate member port (30) can be aligned with the flow passages. The stem extension (78) has an annular shoulder (116) to provide a metal-to-metal seal with the bonnet (36) in the closed position of the gate valve.

High-voltage junction-gate field-effect transistor with recessed gates

Abstract: A new recessed-gate structure for vertical-channel junction field-effect transistors (JFET's) is described together with a self-aligned gate-source process developed to fabricate these devices. Using this technology, devices with groove depths ranging from 8 to 18 µm have been fabricated. The characteristics of these devices is described as a function of the groove depth. It has been found that the devices display pentode-like characteristics at low gate voltages and triode-like characteristics at high gate voltages. The blocking gain has been found to increase with groove depth. However, this is accompanied by an increase in the on-resistance and a decrease in the saturated drain current. Devices with gate breakdown voltages of up to 600 V have been fabricated with the recessed-gate structure. These high-voltage field-effect transistors (FET's) have a unity power gain cutoff frequency of 600 MHz and gate turn-off times of less than 25 ns.

Complementary FET ripple carry binary adder circuit

Abstract: A binary ADDER stage for producing SUM and Carry signals is constructed with five transistors, an exclusive OR gate and an exclusive NOR gate. The two digits to be added are applied to the exclusive OR gate, the output of which is connected to one input of the exclusive NOR gate and to the gate electrode of a first N-type transistor. The second input of the exclusive NOR gate is connected to a carry input terminal, and the output of the exclusive NOR provides the sum of the two digits plus the carry. The conduction path of the first N-type transistor is connected between the carry input and carry output terminals and is conditioned to conduct when the input digits differ. Second and third N-type transistors are serially connected between the carry out terminal and ground reference and have respective gate electrodes connected to the two digit input terminals respectively, for clamping the carry out terminal to a logic 0 whenever both input digits are logical 1's. Fourth and fifth P-type transistors are serially connected between the carryout terminal and positive supply potential and have respective gate electrodes connected to the two digit input terminals, respectively, for clamping the carry output terminal to a logic 1 whenever both input digits are logical 0's.

Locally doubled storage device

Abstract: PURPOSE:To evade the interruption of a system by irreducible necessary local doubling by using optional one of modules in a main storage device as a backup module for doubling. CONSTITUTION:For example, the 1st module selection register 13 is set to (01) and the 2nd module selection register 20 is set to (11). In this case, when (01) is selected by an address register 10, the output 102 of a decoder 11 goes up to (1). Once the terminal S of a storage module 42 is set to (1) through an OR circuit 27, an input to an AND gate 25 is set to (1) through an AND circuit 16 and an OR circuit 19, and then ANDed with the output 119 of a decoder 21 to hold the output 124 of the AND gate 25 at (1), so that the terminal S of a storage module 44 also goes up to (1).

Lens driving device using oscillatory wave motor

Abstract: PURPOSE:To lighten a lens driving of a manual operation time and to improve the manual operability without making a structure complicated by setting a friction contact of a fixed body and a moving body of the manual operation time to a dynamical friction state, reducing a coefficient of friction, and also reducing a contact area. CONSTITUTION:When an electrical operation/manual operation changeover switch 31 is turned on, and a manual driving is selected, an electrical operation/manual operation switching circuit 36 outputs a switching signal of a low level, therefore, an output of an OR gate 47 becomes a high level, and a switching transistor 54 is turned on. On the other hand, an output of an AND gate 48 becomes a low level, and a switching transistor 53 is turned off. Accordingly, high frequency power is supplied to only an electrostrictive element 3a. Therefore, a standing oscillatory wave is generated in a fixed body 2, and a friction torque of the fixed body 2 and a distance adjusting ring 21 becomes small. When the electrical operation/manual operation changeover switch 31 is turned off, and the electrical driving is selected, the electrical operation/manual operation switching circuit 36 outputs a switching signal of a high level, therefore, the AND gate 48 is closed. This switching signal is inverted by an invertor 37, becomes a low level, and it is inputted to an input terminal C of a distance measuring circuit 35.

Recording and detecting device of synchronous information in optical disc

Abstract: PURPOSE:To assure the detection of a correct synchronizing signal even if there is an error in a recording medium, by detecting the coincidence of a readout signal and the reference signal of a synchronizing pattern or combined synchronizing patterns and performing logical processing with majority decision. CONSTITUTION:A signal 50 read out from a disc is inputted to a shift register 6 of the same number of steps as the number of symbols forming the combined synchronizing patterns controlled with a reproducing clock 51. The output of the register 6 is decoded with a decoder 7 according to whether said output coincides with the reference signal forming the pattern of the combined synchronizing patterns in a symbol unit. The decoded output is inputted to a majority decision logical circuit 8. When the majority decision wherein the number of coincidence is a prescribed number or above is held, the circuit 8 generates a detection signal which is outputted as a synchronizing detection signal through an AND gate 90 controlled by a gate signal 91 and the clock phase signal 93 corresponding to the specific phase generated by the synchronizing signal. Even if there is an error in the recording medium, the detection of the correct synchornizing signal is assured by such constitution which performs the logical processing with majority decision.

Heat sensitive gate valve

Abstract: A manually operated gate valve having a fusible element located exterior of the shaft sealing element. Melting of the fusible element permitting outward movement of the shaft and gate elements with all the movable elements being confined to the housing.

Static induction type semiconductor device

Abstract: In a static induction type semiconductor device comprising a semiconductor region having one conductivity type and a low impurity concentration and gate regions having an opposite conductivity type and a high impurity concentration formed in the semiconductor region to thereby define a channel region between these gate regions, there is provided a subsidiary semiconductor region having the one conductivity type and a relatively high impurity concentration either around each gate region to leave an effective channel region in the semiconductor region, or adjacent to the effective channel region in the entire channel region on the drain side. By so constructing the device, this effective channel region has a relatively low potential difference even when the channel region is completely depleted, and provides a relatively wide current path. The subsidiary semiconductor regions establish a relatively high potential difference near the gate regions so that the distance between the gate regions can be made substantially small. In case the subsidiary semiconductor regions are provided around the gate regions, the built-in potential at the junction will become large so that, even at the time of forward biasing, the minority carrier injection from the gate to the channel will become small. Also, this composite channel structure can be effectively applied to recessed gate device and split gate device as well.

Josephson junction latch circuit

Abstract: A Josephson junction latch circuit is provided which has an AND gate having plural inputs and a single output. The output of the single AND gate is directly coupled to a Josephson junction flux storage loop capable of storing flux indicative of the output of the AND gate. A Josephson junction sense line is provided capable of sensing the flux condition of the flux storage loop. The sense line is directly coupled to amplifying gates which produce amplified true and complement quantities whenever the sense line is actuated.

ROM/PLA Structure and method of testing

Abstract: An improved integrated ROM/PLA structure which is capable of simultaneous PLA and ROM addressing substantially reduces the number of tests needed to verify the complete structure. The OR gate matrix and the ROM addressing mode of the AND gate matrix are verified using the ROM addressing mode. The PLA addressing mode is tested by the simultaneously using the ROM and PLA addressing modes to individually activate the AND gates. The AND gates are then tested with the DON'T CARE address lines at a first state and then a second logic state. The test sequence then includes complementing the CARE lines one at a time. The ROM/PLA structure is also improved to include two input structures providing parallel inputs to the OR matrix and dedicated first and second ROM portions of the OR matrix. The output logic is modified so as to merge the literal from the input macroinstruction into the output microinstruction. Similarly, an improved next address logic is provided such that the next address is a function of the output of the OR gate, the microinstruction input, the current computer status and test word input.

Data transfer system

Abstract: PURPOSE:To detect the completion of data tansfer without using an end code by providing one redundancy bit to each of (m) stages of a serial memory, and then applying an OR signal regarding a strobe signal and a data end signal during data writing operation. CONSTITUTION:To a serial memory 1 wherein (n)-bit data are stored as (m) stages, redundancy bits 2 of one-bit constitution are added as (m) stages. During data writing operation, an input ready signal IR is supplied from the memory 1 to a data transmission side, and input data DI1-DIn and a strobe signal ST are applied to an OR gate 3. The gate 3 supplies a shift-in signal SI to the memory 1 and the input data are shifted to right successively. Once transmitted data are all written, a transfer end signal E is applied to the 1st stage of the bit 2 and the gate 3 to perform right shifting operation. When a shift-out signal SO is applied from a reception side, output data DO1-DOn are sent out and after all the data are outputted, the output of the (m) stages of the bits 2 and an output ready signal OR are applied to an AND gate 4, which supplies an end detection signal ED to the reception side.

Data transmission system

Abstract: PURPOSE:To facilitate looping-back operation in case of a fault by doubling a transmission line and then monitoring a synchronizing signal. CONSTITUTION:If a loop transmission line 7 is broken, no synchronizing signal is outputted from a receiving circuit 311 after the breaking of the line, so a monitoring circuit 313 outputs a fault signal a prescribed time later to cut off an AND gate 325, thereby selecting the output of a receiving circuit 321 as the output of a switching circuit 312 by a control circuit 314. When a transmitter 3 enters into a passive loop-back mode, no synchronizing signal is transmitted to a transmission line 8 and a monitoring circuit 223 sends out a fault signal a prescribed time later, so that a transmitter 2 enters into an active loop-back mode. In this mode, a control circuit 224 leads the output of a data processing circuit 217 to an AND gate 225 through a switching circuit 222. Thus, when the transmitters 2 and 3 enter into the active and passive loop-back modes, respectively, a loop-back connection state is set as shown by dotted lines in the figure and data transmission is carried out between optional transmitters.

Manufacture of semiconductor device

Abstract: PURPOSE:To shorten the process of manufacture as well as to obtain the stabilized characteristics for the subject semiconductor device by a method wherein, before gates are formed, the thickness of the expected position where the first gate will be formed is provided thinner than that of the expected position where the second gate will be formed CONSTITUTION:Photoresist 1 is applied to a GaAs 100, an aperture is provided on the expected position, where the second gate will be formed, and in the vicinity thereof, and an active layer 3 with the desired thickness is formed Then, the resist 1 is removed, an SiO2 film 4 is coated on the whole surface, and the above SiO2 film is removed excluding the expected position, where the second gate will be formed, and the vicinity thereof Then, an SiO2 layer 5 is coated on the whole surface, photoresist 6 is applied, an aperture is provided on the positions 7 and 8 where the first and the second gates will be formed Then, the layer 3 of the expected position 7 is formed in the required thickness, and gate recess structure is formed Subsequently, the exposed layer 4 is removed, and the GaAs 3 of the expected position is exposed Then, a gate metal such as Al, for example, is coated on the whole surface, the Al on the resist 6, excluding the aperture, is removed and the first gate 9 and the second gate 10 are formed Accordingly, the interval between the gates 9 and 10 can be always maintained constantly, and the source resistance can also be reduced by the recess structure

Data processing system

Abstract: PURPOSE:To speed up data processing efficiently by determining the priority of the acquisition of an interleaving bus at a high speed. CONSTITUTION:An FF45 sets in response to the fall of the output of an AND gate 44, and subsequently the Q output also changes. The Q output of the FF45 outputted as a request signal L for the exclusive use of an interleaving bus 24 to a priority deciding circuit 33 via an OR gate 46. Consequently, the priority deciding circuit 31 indicates that the request for the exclusive use of the interleaving bus 24 for access to a memory bank 22 is sent. In addition, it is evident from the set state of an FF41 that the access request from a CPU25 to the memory bank 22 is accepted.

Cmos output circuit

Abstract: PURPOSE:To vary respective delay times of driving CMOS circuits for respective channels of a CMOS output circuit, to reduce a current which flows through the CMOS output circuit, and to reduce the generation of a power supply noise, by adjusting the gate width and gate length of each driving CMOS circuit. CONSTITUTION:The gate width/gate length ratios of driving circuts Qp1 and Qn1 for a P channel transistor (TR) Qp3 of the output circuit are set to 39:2 and 8:2, and those of driving circuits Qp2 and Qp3 for an N channel TRQn3 of the output circuit are set to 8:2 and 39:2. Consequently, when they are equal in gate length, Qp1>Qp2 and Qn1

Flash emitting device

Abstract: PURPOSE: To illuminate light of the color temp. or spectral distribution characteristics conforming to the conditions of use in either case when a flash emitting device is used as a main light source or as an auxiliary light source, by controlling the quantity of the light to be emitted by each light emitting source so as to provide the quantity of the light corresponding to the results of arithmetic operations for the ratio of the quantity of emission light to be emitted from each light emitting source according to the color temp. data of an object or a film while providing the plural light emitting sources having mutually different spectral characteristics for emission light. CONSTITUTION: The X contact S 3 of a camera is connected through terminals JB 2 , JS 2 and an inverter IN 4 to the input terminal of a one-shot circuit OS 4 in a control circuit 13 for light emission, and the output terminal of the circuit OS 4 is connected to one input terminal of an AND gate AN 1 . The output terminal of a detecting circuit 8 for completion of charging is connected to the other input terminal of the AND gate AN 1 . A +V power source is connected through a resistor to the connection point of the terminal JS 2 and the inverter IN 4 . The output terminal of the AND gate AN 1 is connected to the set input terminals of a flip-flop FF 0 and a flip-flop FF 1 respectively. COPYRIGHT: (C)1983,JPO&Japio

Back-up system of control computer for efi engine

Abstract: PURPOSE:To maintain the normal running of an engine by outputting a fuel supply timing signal corresponding to the revolution of the engine when the power source voltage drops below the predetermined level CONSTITUTION:When a battery voltage detector 1 detects the voltage drop of the battery voltage V below the standard voltage Es, an AND gate 2 is closed and an AND gate 3 is opend thereby cutting off the fuel injection signal T; from the computer and suppluing the fuel injection signal Tg from the back-up system to a driver 5 through the AND gate 3 and an OR gate 4 Thus, the normal running of the engine is maintained

An event driven approach for mixed gate and circuit level simulation

Abstract: A new algorithm for mixed gate and circuit level simulation is described. I he algorithm* is b.ised on n modular view of electronic networks in which individuri modules nuiy be described cillicr al die ciicuil or at the lo^ic level. Consistency is ensured by employing a novel logic gate model which is derived by abstraction from the underlying (and more detailed) circuit model. Computational efficiency is achieved'by exploiting temporal sparsencss both for circuit and logic level modules through the use of event driven techniques. The implementation of the algorithm in the SAMSON program is briefly described and a sample simulation example is presented.

High speed-low power GaAs/AlGaAs TEGFET integrated circuit

Abstract: Two-dimensional electron gas FETs (TEGFETs) have been used to fabricate DCFL circuits. The MBE wafers are processed as-grown without any recessed gate etching nor self-aligned implantation. Source, drain and gate are directly deposited on the wafer to realize enhancement-mode FETs whereas loads are ungated transistors. With delay times of 18.4 and 32.5 ps at 300 K for 0.9 and 0.032 mW respectively, TEGFETis the fastest semiconductor device amd present very low power dissipation. It is shown that these performances are still limited by contact resistance and material quality. Improvements of these parameters will lead to delay time of ∼9 ps at 300 K for 0.7 \micro m gate length. The high performance and the simplicity of the process involved, make the TEGFET very suitable for LSI/VLSI applications.

Bidirectional transition counter with threshold output

Abstract: A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.

Digital clipping circuit

Abstract: PURPOSE:To clip a signal level in a proper range, by substituting other value for an addition result, in case when an addition result of a chroma signal and a luminance signal has been decided as overflow or underflow CONSTITUTION:When an addition result of a chroma signal 1a and a luminance signal 1b is an overflow in an adder 1, a carry output CO is provided to an AND gate 4 through an AND gate 3 and an inverter 5 The AND gate 3 takes AND of an inversion signal of MSB of the chroma signal 1a, and CO, and substitutes all ''1'' for an addition result if 1a is positive and CO is ''1'' In case when the addition result is smaller than a lower end value N, said gate substitutes N for the addition result If the chroma signal 1a is negative and also the carry output CO is ''0'', the addition result is decided as an underflow, and N is substituted for the addition result