Showing papers on "AND gate published in 1984"

Method of making vertical channel field controlled device employing a recessed gate structure

Abstract: A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.

DC and microwave models for Al x Ga 1-x As/GaAs high electron mobility transistors

Abstract: Models are developed for the dc I-V curves and microwave small-signal parameters of the Al x Ga 1-x As/GaAs heterojunction field-effect transistor, called the high electron mobility transistor (HEMT). An analytic velocity versus field model is used, along with the exact variation with density of the GaAs two-dimensional electron gas Fermi level. A numerical integration is used to obtain the drain voltage for a given gate voltage and source-drain current. The resulting I-V curves are in excellent agreement with the experimental data from four different groups. This model is also used to calculate the transconductance and gate capacitance, and a model is developed for the source resistance. These are used to calculate f_{\max} , the maximum frequency of oscillation, for a range of values of gate length, of AlGaAs alloy composition and doping, and of the thickness of the undoped A1GaAs spacer layer. The results are compared with measured data for HEMT's as well as for a similar GaAs FET with 0.35-µm gate length.

Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs

Abstract: Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the basis of input limitations, circuit complexity, and gate delays. It is shown that TSC comparators cannot exist under two sets of conditions associated with 1-bit input vectors and two-level circuit realizations.

Multi-level arbitration system for decentrally allocating resource priority among individual processing units

Abstract: A decentralized arbitrator includes an individual elementary arbitrator and a level elementary arbitrator for each arbitration unit. Determination of the priority due to one unit, when no other unit claims priority, is accelerated by directing the request states of all units on the same level and on all other levels to the input of an AND gate, the output of which is connected to the bus-utilization enablement input of the relevant unit, through an OR gate and a D flip-flop.

Thin film transistor array

Abstract: PURPOSE:To improve considerably the yield of a TFT array by providing two TFTs per one picture element and connecting their gate electrodes to two scanning lines which are adjacent to each other with the picture element between them. CONSTITUTION:Two TFTs (T21A and T21B) are provided for one picture element (for example, C21), and their sources are connected to a common signal line Y1, and gates are connected to scanning lines (X2 and X3) which are adjacent to each other with the picture element between them, and drains are connected to the picture element electrode of the picture element C21. If short-circuit occurs between the gate and the source of the TFT T21B because of a process defect, a line defect is generated to make an evil case. At this time, the gate of the TFT T21B is disconnected from the scanning line X3. The method where a laser beam is irradiated to the gate part to evaporate a metal of the gate connecting part, or the like is used as the disconnecting means, and the gate of each TFT is so formed that it is easily cut in a connection part 28 to the scanning line.

Semiconductor storage device

Abstract: PURPOSE:To easily detect an address of a cell from the external by providing an output circuit which uses one external terminal other than the address terminal to output the detection signal of a detecting circuit to the external and a mode switching circuit which validates the output circuit only when a test signal is applied to another external terminal. CONSTITUTION:At the test time, a voltage higher than that for normal operation is applied to a terminal 6 to set the output of a mode switching circuit 3 using a high voltage detecting buffer BUF0 to the high level. Though the output of a buffer BUF1 of the normal operation mode is set to the high level also, an output the inverse of CE of an AND gate AND10 goes to the low level because the output of an inverter INV1 goes to the low level. Simultaneously, an output the inverse of OE of an AND gate AND11 goes to the low level, and therefore, the memory is set to the read mode. In case of S=1 (presence of error), the output of an inverter INV3 goes to the low level and is outputted to the external through a terminal 7 to indicate the presence of error; but in case of S=0 (absence of error), the output of an inverter INV2 goes to the high level. Thus, the address of an error bit is easily detected from the external.

Applications of all-optical switching and logic

Abstract: In this paper I review the present status of all-optical switching and logic elements. I then discuss their future potential, taking account of limitations imposed by materials, considerations of system architecture, and fundamental physical mechanisms. I conclude by describing two areas in which all-optical signal-processing systems are likely to have a major impact.

A vertical-type MOSFET and method of fabricating the same

Abstract: A vetical-type MOSFET having high switching capabilities is shown. The high switching speed is facilitated by reduce the capacity between the drain and gate without providing adverse effects on the advantages based on the double diffusion method. The FET is constituted so that the distance between gate electrode and drain region is larger than the distance between the gate electrode and well region functioning as channels.

Analog to digital converter

Abstract: An analog to digital converter uses an integrator having an input to which is applied the unknown voltage to be converted. An opposing reference voltage is switched by a switch means between positive and negative levels to cause the integrator output to ramp up and down between two levels to produce a periodic sawtooth waveform. The sawtooth waveform is applied to a hysteresis comparator which changes its output state when the sawtooth wave form magnitude equals the upper and lower hyteresis levels of the comparator. The output of the comparator is arranged to trigger an edge-sensitive "D" flip-flop. A fixed frequency clock signal from a clock signal source is applied to a clock input of the flip-flop to switch the flip-flop in combination with the output from the comparator. An output signal from one side of the flip-flop is applied as an actuating signal to the switch means to switch the reference signal level. An output signal from the other side of the flip-flop as well as the clock output from the clock signal source is applied to a 3-input AND gate to be combined with an output from a frequency divider arranged to divide the clock signal by a predetermined number. Thus, the operation of the AND gate between its open and closed states is synchronized with the occurrence of the clock signal. The output signal from the AND gate representing the clock signals passed through the AND gate is applied to a counter to be counted. The total number of clock pulses counted during the time period during which the AND gate is open is representative of the amplitude of the input signal to be converted. The stored count from the counter is periodically read out by an output signal from a control circuit triggered by the output from the frequency dividing circuit.

Design Criteria for a High-Dose MOS Dosimeter for Use in Space

Abstract: In a previous paper a small, light-weight, low-power integrating dosimeter is described that is designed for use aboard satellites where the expected total dose is below 30 krad. The radiation-detecting sensors employed are radiation-soft, PMOS transistors. The dosimetric parameter utilized is the shift in threshold voltage, ? VT. This voltage shift is related to the radiation dose absorbed, D, in the SiO2 gate oxide of the transistor. The relationship between ? VT and D is determined with a calibrated Co-60 gamma-ray source. The present paper gives experimental results from which design criteria are derived that will extend the use of the dosimeter into the megarad range. The data show that the existing PMOS transistors can be operated in either of two ways. With a high positive gate bias during irradiation, and with some circuit modification, the PMOS transistors are useful up to about 50 krad. When the source, drain, and gate are grounded during irradiation, and subsequently read out normally, the devices are usable up to approximately 2.5 Mrad. The underlying device physics for these two modes of operation is discussed.

Enhancement of hot-electron currents in graded-gate-oxide (GGO)-MOSFETs

Abstract: Graded-Gate-Oxide(GGO)-MOSFETs with various degrees of gate-drain(source) overlap (and grading thickness of the gate oxide near the polysilicon-gate edge) have been investigated for hot-electron generation. Compared with a conventional MOSFET, the GGO-MOSFET exhibits higher substrate and gate currents when the gate voltage is raised above a critical value(Vgc). Vgc is found to be dependent on the drain voltage. It is also a smooth function of the degree of gate-drain(source) overlap which can be controlled by the fabrication process. These experimental findings are supported by results obtained from the two-dimensional analysis of a similar device structure. Implications of the GGO phenomena on MOS technologies are discussed. Possible use of the GGO-MOSFET in EPROM is proposed.

Magnetic recording and reproducing device

Abstract: PURPOSE:To complete assuredly loading operation, by detecting electrically the end position of the loading operation, and feeding back the result to complete the loading operation CONSTITUTION:When a loading button is pushed, a switch 23 opens temporarily to feed pulses to a gate circuit 25 and an amplifier 30 A motor 31 is revolved with an output, and a loading mechanism moves up to a prescribed position Then the shift of the loading mechanism is stopped by a stopper (not shown in the diagram), and the current of the motor 31 increases suddenly This change is detected by a magnetic sensor 32 and compared with the reference voltage of a wind comparator 34 after passing through an amplifier 33 The current change of the motor exceeds the reference voltage during a spike current is flowed and when a loading operation is over Therefore, a signal of an H level if delivered from the comparator 34 and supplied to an AND gate 28 A mono-multi 29 outputs pulses by the H-level signal and the pulse fed to the gate 28 by the input of a gate 25 The pulse of the mono-multi 29 is fed to a current amplifier 30, and the current supply can be stopped to the motor 31

Synthetic CMOS static logic gates

Abstract: A multi-input CMOS integrated circuit gate is made with fewer PFETs connected between the source voltage and the output node than there are inputs. In many cases only a single PFET is employed. The inputs are applied through a logic network connected to the gate of the remaining PFET. The gate exhibits reduced parasitic capacitance, better PFET-NFET size ratios, and higher speeds.

Piezoelectric ultrasonic apparatus and method for determining the distance from a predetermined point to a target

Abstract: A distance-determining detector and method. A piezoelectric ultrasonic transceiver sends out pulses and receives their reflection and produces an analog output and a trigger output. The analog output is given effect only when it exceeds a threshold level, as shown by a comparator. The trigger output is used for disabling detection during transmission of the transmitter pulse and for producing a time interval during which the analog output is valid, when enabled. An AND gate is connected to the comparator and to the enabled trigger output. Clock pulses are counted, and a flip-flop circuit is connected to the counter and to the output from the AND gate. A multiplying digital-to-analog converter is connected to the flip-flop circuit for determining the distance. There may also be temperature compensation and scaling for the converter for validating the output thereof over a wide range of temperatures.

Semiconductor storage device provided with logical function

Abstract: PURPOSE:To lighten the load of a CPU side and reduce the processing time, by installing a logical operation circuit and logic controller to a memory side and giving a simple operational function which can be executed at one memory cycle to the memory side CONSTITUTION:Data A read out at the preceding time from a memory cell array 21 are stored in a data register 29 A logical operation circuit 30 has a simple operational function which can be executed by 1-step instruction The data inputs are the preceding data A from the register 29, current data B read out from the memory cell array 21, and external data C given from a CPU1 side A logic controller 31 gives an instruction that what kind of operation must be performed on which data to the logical operation circuit 30 depending on the content of a logic bus between a memory and the CPU The operated result of the circuit 30 is written in the memory cell array 21 through a write buffer 28, I/O gate 23

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce the number of contacts, and to miniaturize and integrate a semiconductor device containing an inverter circuit by using an enhancement type transistor as an Mo gate and a depletion type transistor as an Al gate. CONSTITUTION:An Mo layer is formed on the whole surface of a P-type silicon substrate 9, an Mo gate electrode 17 is formed on a gate oxide film 13 in a transistor region 11, which must be formed to an enhancement type through etching, while an Mo mask 18 coating a gate oxide film 13 in a residual transist or region 11, which must be formed to a depletion type, and Mo wiring 19 are formed, N-type As , P , etc. are implanted and source-drain regions 14 in the transistor region 11, which must be formed to the enhancement type, are formed again through self-alignment, and gate length is determined. An inter-layer insulating film 20 is formed on the whole surface of the substrate 9, the insulating film 20 on the Mo mask 18 and the Mo mask 18 are removed, and an N type impurity, such as As , P , etc. is implanted through the gate oxide film 13 to form the transistor region 11 to the depletion type. Al Wirings 23 to the source-drain regions 14, etc. are formed while an Al gate electrode 24 is formed on the gate oxide film 13 in the depletion type transistor region 11.

Inverter function logic gate

Abstract: A bipolar logic gate is provided which will perform logical operations involving the complement of one or more input signals. The gate resembles the conventional ECL OR/NOR gate circuit except that a level shift input transistor is substituted for the standard reference transistor and shifts the voltage level of the input signal whose complement is to be included in the logical operation. A voltage shift of about -0.4 volts occurs either at the base or on the emitter of the level shift input transistor. As a consequence of the voltage shift and subsequent comparison with unshifted voltages, the input voltages are compared with each other rather than with a reference voltage, V BB . Logically, the complement of the input is included in the OR'd and NOR'd outputs provided on the output lines. The logic gate may be incorporated in combinational and sequential logic circuits.

Constant upstream level gate

Abstract: An upstream canal flow control device comprising a gate depending down into the flowing stream from a pivotal axis transverse to the stream and an arm extending downstream from the axis and gate containing a ballast to force the gate against stream flow, the ballast adjustable along the arm to cause the gate to retain an upstream water level as a function of the ballast position therealong.

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

Abstract: The dielectric degradation phenomena in gate oxides of MoSi2/thin n+poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi2, and the SEM or TEM observations of textures of MoSi2, poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi2deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi2/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi2deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi2were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.

Debounce circuit providing synchronously clocked digital signals

Abstract: An improved debouncer circuit is disclosed for providing debounced, synchronously clocked digital signals from a single-throw switch, as for instance, of the momentary contact type. A signal, variable between two logic levels, is provided by the switch for input to the debouncer circuitry. That input signal is applied as one input to an EXCLUSIVE OR gate, the other input to that gate being fed back from the Q output terminal of an output data latch having complementary Q and Q* output terminals. A signal representing the Q* output terminal of the data latch is connected to the D input of that latch such that a synchronous latch clocking signal appearing at the clock input of the output data latch serves to toggle the states of the Q and Q* output terminals. The signal appearing at either one of the output terminals Q, Q* of the output data latch may be used as the debounced signal provided to other circuitry, depending upon signal polarity needs. The clocking signal which toggles the output data latch is the output of a NAND gate. The inputs to the NAND gate include one phase of a two-phase synchronous clock signal, the output of the EXCLUSIVE OR gate, and the signal from the Q output of a second data latch. The second data latch is clocked by the other phase of the two-phase synchronous clock. The D input of the second data latch is connected to the output of an AND gate, with the inputs to the AND gate being provided by the O* output of the second data latch and by the output of the EXCLUSIVE OR gate.

Dynamic flip-flop with static reset

Abstract: A D-type flip-flop (10) receives the D input on an input line (14) of a transfer gate (12) that also receives the flip-flop clock signal. A state gate (20) forwards the transmission-gate output when the signals on two of its input lines (22) and (24) remain true. To reset the flip-flop asynchronously, a false signal is imposed on one of the input lines (22) of the state gate (20). By coordination of a second clock signal, which is applied to a second transmission gate (34), with the reset signal, the reset condition is held until the next clock pulse on the first transmission gate (12). The flip-flop ordinarily operates as a dynamic circuit, but, in order to maintain the reset condition in circumstances in which the reset state is to be maintained for an extended period of time, a latch gate (26) is enabled by a true signal on one of its input lines (32) to feed the reset output of the state gate 20 to one of its input terminals (24 ) so as to latch the flip-flop in the reset state.

Error protection apparatus

Abstract: A Reed-Solomon error correcting apparatus is programmable to perform several distinct error correction functions, namely, encoding, error detection, syndrome generation, burst error trapping, and Chien searching. The apparatus essentially comprises a set of two t registers (30) where t is the number of errors to be corrected, a set of two t exclusive-OR gates (32), a set oftwottop multiplexers (34), a set of two t bottom multiplexers (36), a first set of two t Galois Field multipliers (S0-S19), a second set of two Galois Field multipliers (G0-G19), a feedback multiplexer (42), a lead exclusive-OR gate (40), an AND gate (46), t-1 ordered Chien exclusive-OR gates (52) and a controller (12).

Ripple-borrow binary subtraction circuit

Abstract: A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate which has a second input connected to a borrow input signal. The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal is generated with the combination of a pass transistor coupled between the borrow input and borrow output terminals and a three state logic circuit which has its output termial connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.

Characteristics and reliability of the SEPROM cell

Abstract: A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSI's with higher packing density, since the area of the second gate oxide is equal to that of the first gate oxide. To improve the coupling capacitance ratio, which relates to write and read operations, a thin second gate oxide is required for the SEPROM cell at a risk of degradation in charge retention characteristics. A measured test device, however, shows sufficiently good characteristics both in programming and charge retention, due to the desirable structure of the cell. The SEPROM structure appears to be practical and promising for both EPROM and logic device applications.

Integrated circuit for oscillator

Abstract: PURPOSE:To select one of a CR oscillator or a crystal oscillator by providing the crystal oscillator and the CR oscillating circuit and controlling a signal switching gate selecting one of the outputs with a signal given to a pin led out externally from an integrated circuit. CONSTITUTION:The signal switching gate 3 is provided to the crystal oscillating circuit 1 and the CR oscillator 2. In selecting the crystal oscillator, a crystal oscillator X is inserted between pins P1 and P2, the pin P1 is connected to a reference potential via a capacitor C2, the pin P3 is connected to the reference potential, a negative power supply Vss is connected to the reference potential so as to give an L level signal to a pin P5 as a switching input C and an output A of the crystal oscillating circuit is extracted. In selecting the CR oscillator, the pins P1, P5 are connected to the reference potential and a resistor R4 in response to a desired oscillating frequency is inserted between pins P3 and P4. Thus, the crystal oscillating circuit is made inoperative, an AND gate AND1 is turned off, an AND2 is turned on and an output B of the CR oscillating circuit is taken as the selected output H.

Error isolator for bi-directional communications buses

Abstract: A communication bus user design that significantly reduces the likelihood of bus disablement. Request to transmit received by a user are validated in the communications processor and by an interlock circuit. Logic signals generated in response to the two validations are coupled to an AND gate, wherefrom an enabling signal is coupled to an amplifier when the two logic signals coincide. Communications signals from the communications processor are thereafter coupled via the amplifier to the bus.

Magnetic tape controller

Abstract: PURPOSE:To attain reduction in the occupying time of a channel by providing a data buffer storing read medium identification information so as to attain execution of a forward reading instruction without any instruction from a high- order device after the end of tape loading. CONSTITUTION:When a forward reading instruction is incoming from the channel side, since a data read control circuit 3 is in the operationable state and an AND gate 14 is opened, a data in a data buffer 2' is transferred to the channel. When the transfer of data is finished, a data end signal is reported to the channel. Even if the forward reading intruction is given in this way, when a mount end signal is given before, since a forward reading instruction suppressing latch 10 is in set state, an AND gate 13 blocks the forward reading instruction from being propagated to a signal line 24. Thus, no forward drive command signal to a magnetic tape device exists and neither a data write control circuit 4 nor a reading control circuit 5 is activated in this case.

Decoder circuit for a static random access memory

Abstract: A decoder circuit for a static random access memory cell and which may be integrated in monolithic form using gallium arsenide field effect transistors. The circuit comprises a first logic NOR-gate P1 having (n+1) inputs on which the n coded memory address signals or their complements are received, and also the chip-enable selection signal SB. The gate P1 is connected by a load resistor R to a supply voltage VDD1. A second NOR-gate P2 receives the same inputs as the gate P1 and has as its load a transistor T0 the gate electrode of which receives the output of the gate P1 and the drain of which is connected to a power supply voltage VDD2 which is less than VDD1. The voltage VDD2 is also the supply voltage for the memory cell, and is set at the clipping value of the gate junctions of the constituent transistors of that cell. The output VS of the decoder is produced at the drains of the transistors forming the second NOR-gate P2 which are connected to the source electrode of the load transistor T0. The inputs of the NOR-gates receive a chip-enable selection signal SB after application of the n coded memory address signals, thereby achieving reduced access time for the memory cell.

Ground speed determining radar system

Abstract: A ground speed determining radar system for take off roll and landings and roll out maneuvers has a ground based modulating radar reflector and a carrier based radar. The radar transmits microwave energy to the reflector where it is modulated by rotating spaced reflectors and returned to the radar receiver. The receiver is a heterodyne receiver having a log IF stage and a fast time control (FTC) circuit for attenuating clutter and an acquisition loop circuit, lock-on circuit and tracking loop circuit. The acquisition loop circuit includes a center, gate, modulation bandpass filter, switch, acquisition sweep generator and gate generator; the lock-on circuit adds a delay line and a good data indicator to the loop acquisition circuit, and the track loop circuit includes early/late gates, early/late gate low pass filters, subtractor, integrator, the switch and gate generator. Prior to acquisition or upon loss of lock-on, the modulation band pass filter has zero output to the switch and the switch switches in the acquisition sweep generator and a ramp voltage is applied to the early/late gates. During the time the early/late gates are swept over the desired modulated frequency from the ground reflector the modulated band pass filter outputs a signal to the switch which switches in the integrator of the tracking loop. The lock-on circuit's delay means delays the modulation band pass output a time sufficient for the integrator to settle down and spurious noise to the disappear before activiting the data indicator. At times, the early/late gates are not centered on an echo return; thus more echo energy is in one (late) gate than in the other (early gate), for example. The subtractor outputs the difference to the integrator which output a dc voltage proportional to the range to the reflector. A differentiator and range indicator and the switch are connected to the integrator for receiving its dc output and, respectively, outputting velocity and range information and feed back to center the early/late gates on the echo.

Fast and gate with programmable output polarity

Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.