Showing papers on "AND gate published in 1985"

Programmable logic array with added array of gates and added output routing flexibility

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1 through 102-66). The output signals from the first set of AND gates are programmably elec­trically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are program­mably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coup­led to each of the output signals from the second OR logic array and the output pins (O₁ through O₁₀) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.

Process for forming a T-shaped gate structure

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess. Gate contact metal is then deposited in the opening thus formed and the nitride, photoresist and gold layers are removed, lifting off a portion of the gate metal layer thus leaving a T-shaped gate which provides a minimum length at the channel gate interface and provides a low gate resistance.

Digital frequency divider or synthesizer and applications thereof

Abstract: The digital frequency divider (or synthesizer) produces non-integral submultiples of an input frequency by alternately dividing its input by two integers by means of two integral digital frequency dividers, one of which produces an output higher than the desired non-integral submultiple and the other of which produces an output lower than the desired non-integral submultiple. The desired non-integral submultiple is obtained by alternately switching the circuit output to two integral digital dividers, the duty cycle of the switch determines the precise output frequency obtained. The concept can be implemented with programmable digital counters and logic circuitry. The circuitry can be used to implement a novel method of duplicating an accurate signal with improved stability. A circuit useful in practicing the method measures the ratio of two frequencies. The frequency divider can be used in a multiplexer set to provide an improved digital clock generator and asynchronous buffer which provides improved user clock signals.

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices

Abstract: A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.

Accelerated test apparatus and support logic for a content addressable memory

Abstract: Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.

Trapezoidal-groove Schottky-gate vertical-channel GaAs FET (GaAs static induction transistor)

Abstract: This letter reports, the development of a vertical-channel. GaAs FET with the unsaturated I-V characteristics of the static induction transistor (SIT) and voltage blocking capability up to 100 V. The device structure utilizes the anisotropic etching properties of GaAs, in which the gate regions are formed by a double-angle evaporation into trapezoidal etched grooves. This single evaporation step simultaneously provides both source and gate metallization, and the novel trapezoidal groove geometry automatically yields a self-aligned gate with separation of source and gate onto different levels, thus eliminating the need for critical alignment arising from source-gate interdigitation.

Logic of Discovery and Logic of Discourse

Abstract: Of course, from childhood to forever, we are always thought to love reading. It is not only reading the lesson book but also reading everything good is the choice of getting new inspirations. Religion, sciences, politics, social, literature, and fictions will enrich you for not only one aspect. Having more aspects to know and understand will lead you become someone more precious. Yea, becoming precious can be situated with the presentation of how your knowledge much.

Exclusive OR/NOR gate having cross-coupled transistors

Abstract: A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.

Signal processing device

Abstract: PURPOSE:To decrease surely and effectively noise due to the transient response of a changeover switch in an output signal by forming a binary control signal for pre-value holding and holding the pre-value of the output signal by this control signal. CONSTITUTION:A diode 37 is reverse-biased at a period other than a period T1 so as to make the impedance high in pre-value hold circuits 30L, 30R, the source and gate of a field effect transistor (TR) 33 are made nearly to the same potential, then the TR33 is turned on, and a diode 37 is turned on at the sufficiently short period T1 where noise N exists in sound signals SL and SR, the gate and source of the field effect TR33 are biased by a voltage being a pinch-off voltage or below, the TR33 is turned off, a voltage of a capacitor 35 just before the period T1 is extracted at an output terminal 36, and sound signals SL', SR' from which the noise N is eliminated are obtained at the output terminal 36 of pre-value hold circuits 30L, 30R.

Digital phase meter apparatus

Abstract: A digital phase meter to measure the phase difference between an input signal and a reference signal and output this phase information in the form of an eight bit number. The input signal and the reference signal, which are sinusoidal, are conditioned to a more defined leading edge by a high speed differential voltage comparator and a dual/differential line receiver. A series of uniquely configured D flip-flops are used to detect the leading edge of both the signal input and the reference input. An AND gate then acts as a switch that is activated on the leading edge of the signal input. The time interval between the two positive leading edges of the input signal and reference signal specifies the phase difference. The AND gate is in the high state for this duration. The phase difference is converted into an 8-bit binary number via two 4-bit cascaded counters. The high output of the AND gate is used to enable the counters for the duration of the phase difference.

CMOS Scaling Implications for Total Dose Radiation

Abstract: Scaling of CMOS device channel lengths can result in increased threshold voltage shifts after exposure to total dose radiation. An analytical model has been developed in order to predict these threshold voltage changes as a function of gate length and total dose for both gate oxide and parasitic thick field oxide transistors. Measurements show large increases in threshold voltage shifts after irradiation as gate lengths are decreased. The model is proven accurate to a total dose level of 106 rads (SiO2) and gate lengths down to 0.9 um. Scaling of field oxide gate lengths can have a severe impact on total dose hardness.

VIB-4 the effect of channel length and gate oxide thickness on the performance of insulated gate transistors

Abstract: Good performance in three-terminal devices using am~wphous semiconductor material can hardly be achieved due to low carrier mobility and short life time in the amorphous films. However, the amorphous films are attractive because they offer such fea.:ures as 1) a low-temperature process, 2) easy and inexpensive fabnication, and 3) a wider bandgap than the crystalline material. Recently, a Si bipolar transistor with an amorphous emitter has been t1 ied [l]. A previous study on a solar cell with an amorphous S ic I H/crystalline Si p+-n heterostructure [2] confirmed that good electrical performance can be achieved in such a heterostructure. A s a successive development of this heterostructure, an HBT cons .sting of a-Sic : H emitter and crystalline Si has been realized for the first time and its performance and band structure will be discussed here. Conventional Si process was used for fabrication. A base window was cut into the field oxide formed on a 3-5 fi . cm (111) p s i substrate and 31p+ ions were implanted for base with a dose of 2 X 10” ionskm’. Next, an emitter window (area of 4.18 X em2) was cut into a wet oxide and amorphous S ic : H film was e‘eposited using SiH4, CH,, and BzH6 gases at a substrate tempe:.ature of 450°C in an inductive coupled plasma CVD system. A1 dectrode for emitter was fabricated and using this as a mask the 3-SiC : H film was etched by CF, plasma etching. Finally, the base and collector A1 electrodes were formed. Satisfactory transistor operation was clearly observe1 with a common emitter current gain of 50 at a current density 01’ approximately 2.4 A/Cm2. The hFE-Ic characteristics measured at VcE = 5 V for various temperatures (27OC-97”C) are flat over tEe current range of 10-6-10-4 A without any significant decrease 01’ the gain in the lower current values. The temperature characteris tics show a strong dependence of temperature on the gain, and it increases with increasing temperature. Such a behavior coud be explained by a fairly large activation energy of the emitter material. We could estimate the band structure of a-Sic : H/c-Si heterostruc ture from h,/T-l/Tplots. Considering the electron affinity of a-Si(: : H to be close to that of Si and assuming the bandgap of a-Sic : H t.1 be equal to its optical gap of 1.8 eV [2], it can be deducted from the proposed band structure that the discontinuity of the conduction band AEc = 0.16 eV and that of the valence band A E y = 0.54 eV. A Si p-n-p heterobipolar transistor using an a-Sic : H enlitter has been realized for the first time. We are continuing this study for np-n type as well, in which a higher hFB can be expectec. from the view-point of barrier height difference for holes and e1:ctrons as predicted by the band diagram.

Logic data transfer bus preloading circuit

Abstract: A data transfer bus preloading circuit including a large sized transistor r ensuring rapid bus conductor preloading. This transistor is conductive at the beginning of the preloading step proper, but is blocked as the bus voltage reaches the desired preload value which corresponds to the sum of the respective threshold voltages of two other transistors of the circuit. The circuit includes five field effect transistors, two supply terminals, a preloading control input terminal and a preloading inhibiting input terminal. The large size transistor is connected between a first supply terminal and the output terminal of the circuit. A second transistor is connected between the gates of the first and third transistors. The gate of the second transistor is connected to the preloading control input terminal. The third transistor is connected between the source terminal and the fifth transistor. The gate and source of the third transistor are connected together. The fourth transistor is connected between the ground supply terminal and the gate of the first transistor. The gate of the fourth transistor is connected to the preloading inhibiting input terminal. The fifth transistor is connected between the third transistor and the ground supply terminal. The gate of the fifth transistor is connected to the output of the circuit. It is also possible to add a sixth transistor between the fifth transistor and the ground supply terminal with the drain and gate of this transistor being connected together.

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

Abstract: A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance R s and gate capacitance C g , the shallow n+implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance g m , low source resistance R s , small gate capacitance C g , and small deviation of threshold voltage \part V_{th} , and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To contrive to reduce the occupation area of a semiconductor device by a method wherein an arithmetic control circuit, the fundamental cells of a gate array and so forth are provided on one semiconductor substrate and each element is mutually connected using both of the arithmetic control circuit and the fundamental cells of the gate array so one standard matrix body. CONSTITUTION:For example, an arithmetic circuit 20 consisting of an arithmetic and logic circuit, a register and an interface logic circuit is provided on the central part of one semiconductor substrate 11 and fundamental cells 12 are regularly arranged on the periphery of the arithmetic circuit 20. Moreover, connecting cells 14, each combined with input and output, and input and output pads 15 are provided and a wiring region 13 is formed inbetween each column of the fundamental cells 12. When a wiring layer is made in such a way as to be formed between each element using both of the arithmetic control circuit and the fundamental cells of the gate array as one standard matrix body, the occupation area of the substrate of the semiconductor device completed by integrally forming the arithmetic and logic circuit, the register, etc., and the peripheral circuits, which constitutes a microcomputer in one body, can be suppressed smaller. Moreover, as a gate array and an arithmetic processing circuit are integrally formed in one body on the one substrate, the smallest possible circuit constitution is obtained. As a result, the processing speed of the semiconductor device is remarkably increased.

Thin film active element

Abstract: PURPOSE: To connect electrodes easily at low cost by arranging some of electrodes which constitute a thin film active elements adjacently to other electrodes in an interdigital shape. CONSTITUTION: When the source and gate of the 1st transistor (TR) 6 are short- circuited, a source connection line 12 is disconnected to cut off a potential flow from a source bus line 3 to a gate bus line 9 through the short-circuit point. When a short circuit is found between the gate and drain of the TR 6, the drain electrode 5 and/or gate display electrode 11 are disconnected to prevent a potential flow from the line 9 to the electrode 11 through the short- circuit point. Then, the drain electrode 17 of the 2nd TR 7 is connected to a display electrode for a picture element in an inter-digital shape to supply a source signal of an adjacent picture element to the picture element to prevent a turn-on line defect, a turn-on point defect, and a turn-off point defect. Thus, secure connections are made at low cost. COPYRIGHT: (C)1986,JPO&Japio

Data transfer control system

Abstract: PURPOSE:To improve the reliability for data transfer of a read system between a channel device and an input/output controller of a computer, by using effectively a gap between blocks of data transmitted every block. CONSTITUTION:The lacking number of bytes is first added to the output of an address pointer IOA by an adder 9 in case the number of read-in bytes of a final data buffer DB4 of a block to a channel command word CCW added with a chain data CD flag is lacking for the prescribed byte width for serial/parallel conversion. Then the output of the adder 9 is compared with the output of an end pointer by a comparator 10. Furthermore an AND is obtained through an AND gate 11 between the output of the comparator 10 and the CD flag. Making use of the output signal, a channel device 1 fetches a CCW connected later from a main memory. Then the end pointer is replaced with a pointer added to the number of new bytes of a subsequent CCW.

Microcomputer for timepiece

Abstract: PURPOSE:To make it possible to process a pulse equivalent to a cycle time by switching a chronograph counter to a chronograph mode and a counting mode where the pulse impressed to an external terminal is counted. CONSTITUTION:An oscillating circuit 1 oscillate a reference frequency, and the reference frequency passes a frequency dividing circuit 3, and the output of a 1/(100)-sec pulse generating circuit 4 is inputted to an AND gate 6 controlled by the output Q of an FF5 which is inverted by a signal SW generated in the chronograph mode. A switching gate 7 is controlled by an FF12 set and reset by a control circuit 20 and switches the output of the AND gate 6 and the signal impressed to an external terminal 11 to impress them to a chronograph counter 13. An NOR gate 16 and an NAND gate 19 make a transmission gate 17 conductive by instruction signals IR0-IR15 to transmit the counted data of the chronograph counter 13 to a data bus 18.

Semiconductor memory circuit

Abstract: PURPOSE: To easily evaluate the speed of a memory by feeding back an output of the memory to an address CONSTITUTION: The output of the memory is fed back to one address ADD through an AND gate 2 Memory contents '1' and '0' at respective addresses '0', '1' are previously written in the memory M When a control input terminal CTRL is '0', the output of the memory M is fed back to the address ADD through an AND gate 1, the circuit forms a kind of an oscillation circuit and an oscillation waveform is obtained from the circuit Since an oscillation cycle 1/2(td) can be evaluated as an access time of the memory, the speed of the memory can be easily evaluated by counting up the oscillation waveforms COPYRIGHT: (C)1987,JPO&Japio

Multiple input OR-AND circuit for FET logic

Abstract: An OR-AND logic circuit includes a plurality of OR gates wherein each OR gate includes a plurality of source coupled FETs and the inputs to each OR gate are the control gates of the FETs. A logic node serves as the output for each OR gate. A unidirectional current conducting means, such as a Schottky diode, is connected to each output logic node of each OR gate. One terminal of each unidirectional current conducting means is connected to a common logic node. Current passing through a load means passes through the common logic node and is divided among the unidirectional current conducting means so that a logical AND function is provided at the common logic node with the logic condition at the output logic nodes of the OR gates serving as the inputs to the AND gate. Multiple levels of such OR-AND circuits can be provided with the AND output of one level serving as the input to an OR gate of the next stage.

Glass break detector

Abstract: The sound of breaking glass comprises a low frequency or thump sound at the moment of breakage, followed by a tinkle sound caused by collision of the glass fragments, this sound being of lower amplitude. The invention turns on the discovery that, irrespective of the size and shape of the glass and the characteristics of the surroundings, the thump has substantial low frequency components at about 350 Hz, and the tinkle has substantial high frequency components at about 6.5 KHz. The method of the invention lies in identifying the high and low frequency components in that order and separated by a short time interval. Apparatus according to the invention comprises a microphonefeeding into a high frequency and a low frequency channel. The low frequency channel has a bandpass filter centered on 350 Hz, the output of which triggers a time delay establishing a time window during which a signal is applied to one input of an AND gate. The high frequency channel includes a bandpass filter centered on 6.5 KHz, an output from which is applied to the other input of the AND gate. An output from the AND gate indicates that a signal characteristic of breaking glass has been detected and this output may be applied to trigger alarm circuits. A suitable bandwidth for the high frequency bandpass filter is +/-2 KHz and a suitable delay between the detection of the thump signal and the commencement of the time window is 200 milliseconds.

Controlling circuit of bus circuit

Abstract: PURPOSE:To obtain a controlling circuit of a bus circuit that restrains plural tri-state gates from turning on simultaneously and prevents bus output from becoming indefinite by applying a signal of 0 to an input terminal at the time of test preparation operation. CONSTITUTION:When an arbitrary value is set to FF circuits 4a, 4b at the time of test preparation operation, there is the possibility that all of tri-state gates 1a-1c become on or off simultaneously. In this case, a 0-signal is applied to the input terminal. Consequently, AND gate circuits 7a, 7b become non-conduction state, and 1 is applied to the input end of an OR circuit 8. Accordingly, irrespective of output value of FF circuits 4a, 4b, tri-state gates 1a, 1b become off, and the tri-state gate 1c becomes on.

Interruption control circuit

Abstract: PURPOSE:To prevent a program from runaway due to interruption processing by forming an FF to prevent a non-maskable interruption signal. CONSTITUTION:The FF4 is turned to ''0'' without fail when a power supply is turned on. A decoder 5 decodes an instruction for setting up a stack pointer and sets up the stack pointer to turn the FF4 to ''1''. The output of the FF4 and an interrupting instruction obtained by receiving a non-maskable interruption (NMI) signal to a terminal 1 are inputted to an AND gate 2, and only when both the signals are ''1'', the output of the AND gate 2 is inputted to an interruption accepting circuit 3. In accordance with the output of the AND gate 2, the circuit 3 saves the program in processing to the stack pointer to process the interruption signal. Therefore, the NIL signal is prevented until the stack pointer is set up after turning on the power supply.

Detecting circuit for signal brake

Abstract: PURPOSE: To detect the break of a signal in a semiconductor at an optional point by using a two-input selector which turns on one transfer gate when the signal to a select signal terminal is at a high potential to select a low- potential input, turns on the other transfer gate when the signal is at a low potential to select a high-potential input, and turn on both transfer gates when the signal is at an intermediate potential to generate a low-potential output. CONSTITUTION: The input terminal 7 of a signal break detecting circuit is connected to one input terminal of a two-input NOR gate 8 and further connected to the other input terminal of the two-input NOR gate 8 through an inverter 9. When the signal to the input terminal 7 is ceased and the potential attains to the intermediate potential, all transistors (TR) constituting inverters 9, 11, and 2 and the NOR gate 8 turn on and their output potentials attain to the intermediate potential. Consequently, transfer gates 1 and 2 turn on at the same time. In this case, the TR sizes of the transfer gates 1 and 2 and inverter 6 are so set that the input to an inverter 13 is sufficiently at the level 'L', thereby generating an 'H'-level output at an output terminal 14 only when the input signal is broken. COPYRIGHT: (C)1986,JPO&Japio

Programmable logical array

Abstract: PURPOSE:To realize a small sized and high speed PLA by generating automatically a clock starting the operation of an OR logical section in an optimum time through a dummy circuit similar to an AND logical section in matching with the end of logical operation of the AND logic. CONSTITUTION:The programmable logic array (PLA) of this invention has the dummy logical circuit similar to the AND logical section in addition to the AND logical section and the OR logical section. Then the AND logic is started by a clock phi1, a phi2 generated automatically through the dummy logical circuit starts the OR logic the same time as the end of this logic and the entire PAL operation is finished. That is, the logical processing time of the PLA is from the leading of the phi1 at a time t1 until the voltage decision of output terminals O1, O2 at a time t5, the logical operation is executed continuously and a high speed logical processing time is attained by a single phase clock phi1.

Fault simulation for differential cascode voltage switches

Abstract: A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.

Compound semiconductor switch

Abstract: PURPOSE:To eliminate the need for an individual driving power source and to simplify the circuit constitution of a compound semiconductor switch consisting of series-connected GTO and FET by obtaining the gate power source of the GTO from a main circuit through a circuit consisting of a resistance and a capacitor CONSTITUTION:When the compound semiconductor switch consisting of the GTO1 and FET2 is off, the capacitor 6 is charged through the resistance 8 up to the voltage determined by a constant voltage diode 3 and the FET2 turns on by being applied with a control signal Then, the capacitor 6 is discharged to the gate of the GTO1, which also turns on to turn on the compound semiconductor switch When the FET2 turns off, on the other hand, a load current flows through the anode and gate of the GTO1, a diode 7, and the capacitor 6 or constant voltage diode 3 to turn off the GTO1, turning off the compound semiconductor element

And gate for ecl circuits

Abstract: Die in ECL-Schaltungen ublichen UND-Verknupfungen durch Seriesgating beschranken die Anzahl der Eingangsvariablen auf die Anzahl der moglichen Seriesgating-Stufen, also maximal drei Stufen. The usual in ECL circuits AND operations by Seriesgating limit the number of input variables on the number of possible series-stages, ie a maximum of three stages. Die Erfindung realisiert durch schaltungstechnische Masnahmen zusatzliche UND-Verknupfungen zwischen Eingangsvariablen und ermoglicht pro Gatter mehr als drei Eingangsvanablen und damit kurzere Signallaufzeiten. The invention realized by circuitry measures additional AND operations between input variables and allows per gate more than three Eingangsvanablen and thus shorter signal propagation times.

Coordinate position detector

Abstract: PURPOSE:To obtain a coordinate position input device by obtaining a position detection signal from a switch if the switch exists in a corresponding part on a switch matrix and obtaining the position detection signal from outputs of switches existing on both sides if no switches exist in a corresponding part CONSTITUTION:A physical X coordinate detecting circuit 16 detects turning-on/ off of switches of individual rows of X coordinates of a switch matrix 11 con- sisting of transparent coductive films which are combined to stripe shapes when an optional transparent electrode switch existing physically on the switch matrix 11 is turned on Outputs of AND gates 12 to which pairs of outputs of adjacent rows are inputted to a virtual X coordinate detecting circuit 17, and the circuit 17 detects X coordinates of a virtual transparent electrode switch which is turned on Data values of physical X coordinates and virtual X coordinates outputted from the virtual X coordinat detecting circuit 17 and the physical X coordinate detecting circuit 16 are inputted to an X coordinate detecting circuit 18, and the circuit 18 generates a logical X coordinate value and outputs it

Field effect transistor and manufacture thereof

Abstract: PURPOSE:To increase gate withstand voltage by forming a P-N junction gate in a field effect transistor, which is operated at high speed by utilizing a secondary electron gas and has the same conduction type hetero-junction. CONSTITUTION:A non-doped GaAs layer 1, an N type AlGaAs layer 2, an N type AlGaAs layer 3, the ratio of Al therein is decreased gradually, an N type GaAs layer 4 and lastly a P type AlGaAs layer 5 are grown on an insulating substrate in order from the lowermost section. A mesa is formed for an isolation. A gate electrode section is patterned by using a resist 6, and gate gold layers 7 and 8 are applied in vacuum, thus forming the gate electrode 8. Only the P type AlGaAs layer 5 is etched selectively. A P-N junction gate shorter than the gate length of the gate electrode 8 can be obtained extremely easily through a side etching up to the lower section of the gate electrode 8 at that time.