Showing papers on "AND gate published in 1986"

Design procedures for differential cascode voltage switch circuits

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

Abstract: A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

High contrast, 1.3 μm optical AND gate with gain

Abstract: A high contrast (5:1), 1.3 μm wavelength optical and gate is demonstrated using a bistable Fabry–Perot InGaAsP/InP laser amplifier with large gain. Using simple arguments, it is shown that, subject to realistic constraints, the maximum attainable contrast ratio in a bistable Fabry–Perot logic gate is about 10. Unlike bistable amplifiers, there is a significant trade‐off between contrast and gain in passive devices.

Semiconductor memory device having nibble mode function

Abstract: In the semiconductor memory device havig a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks. Data bus lines are provided separately to each of the first and second cell blocks. Sense amplifiers are provided separately to each of the data bus lines. A column decoder, for connecting between bit lines, is provided in the memory cell array and corresponding data bus lines based on address signals and gate signals in a selection state. A switching circuit is provided for switching between sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and for connecting these sense amplifiers to output buffers. A clock signal generating circuit is provided for generating the gate signals. The gate signals are generated in such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of the column address strobe signal in the nibble mode.

Asymmetrical characteristics in LDD and minimum-overlap MOSFET's

Abstract: An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the I-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive level angle.

An Introduction to GaAs Microprocessor Architecture for VLSI

Abstract: Gallium arsenide, or GaAs, technology has recently shown rapid increases in maturity. In particular, the advances made in digital chip complexity have been enormous. This progress is especially evident in two types of chips: static rams and gate arrays. In 1983, static rams containing 1K bits were announced. One year later both a 4K-bit and a 16K-bit version were presented. Gate arrays have advanced from a 1000-gate design presented in 1984 to a 2000-gate design announced in 1985. With this enormous progress underway, it is now appropriate to consider the use of this new technology in the implementation of high-performance processors. GaAs technology generates high levels of enthusiasm primarily because of two advantages it enjoys over silicon: higher speed and greater resistance to adverse environmental conditions. GaAs gates switch faster than silicon transistor-transistor logic, or TTL, gates by nearly an order of magnitude. These switching speeds are even faster than those attained by the fastest silicon emitter-coupled logic, or ECL, but at power levels an order of magnitude lower. For this reason, GaAs is seen to have applications in computer design within several computationally intensive areas. In fact, it has been reported that the Cray-3 will contain GaAs parts. GaAsmore » also enjoys greater resistance to radiation and temperature variations than does silicon. GaAs successfully operates in radiation levels of 10 to 100 million rads. Its operating temperature range extends from -200 to 200/sup 0/C. Consequently, GaAs has created great excitement in the military and aerospace markets.« less

Programmable logic device

Abstract: A programmable logic device of a single semiconductor chip includes a plurality of programmable AND-OR logic blocks, each block including an AND gate array and an OR gate array and at least a pair of input and output lines; a plurality of input/output buffer blocks, each block including at least one input and output lines; and a plurality of interconnection lines across which the input and output lines extend. A programmable switch is provided at each of the intersections between the input and output lines and the interconnection lines, so that each of the input and output lines are selectively connected to a desired one of the interconnection lines. Preferably, each of the interconnection lines further includes at least one programmable switch so that each of the interconnection lines may be divided into a desired number of segments which are electrically isolated from one another. A programmable logic device may include a plurality of programmable logic unit cells and first interconnecting means for interconnecting the cells, each of the cells including a plurality of programmable AND-OR logic blocks, a plurality of input/output blocks and second interconnecting means for interconnecting the blocks.

Method in the manufacture of integrated circuits

Abstract: A method for manufacturing integrated circuits in which conductors and gate structures are built-up on a substrate plate, the conductors incorporating a layer of polycrystalline silicon and the gate structures including a gate electrode of polycrystalline silicon, where each of the gate structures is surrounded by doped source-and-drain-areas and where the gate electrode and the source-and-drain-areas respectively are metallized by depositing thereon a metal which reacts with the silicon from which the gate electrode and the source-and-drain-areas are comprised, so as to form a silicide layer. In accordance with the invention the gate electrode (3) is metallized in a first process stage. The source-and-drain-areas (18, 19) are metallized in a later process stage. Subsequent to metallizing the gate electrode in the first process stage, a protective layer (5) is applied to the metallized layer (4) of the gate electrode in a second process stage. All layers (16, 13, 7) present on the source-and-drain-areas (18, 19) are then removed to expose silicon, whereafter a metal (8) capable of reacting with the exposed silicon is deposited over the substrate, therewith to metallize (9, 10) the source-and-drain-areas (18, 19). In the second process stage, the protective layer (5) is given a thickness such that subsequent to the aforementioned etching process there remains a given, smallest thickness sufficient to ensure that the deposited metal (8) will not react with the silicon of the gate electrode (3, 4).

Optical binary coded ternary arithmetic and logic.

Abstract: Two ternary, an ordinary ternary (OT) and a binary balance ternary (BT), number representations to be used for optical computing are discussed. An unsigned OT number is represented by a string of symbols (0, 1, 2), while for the BT, the three logic symbols take on the set (−1, 0, +1). The BT symbols can represent a signed number. Using a particular binary encoding method, the three ternary symbols are converted to a pair of binary symbols. The binary coded ternary (BCT) representation has two advantages. First, it allows use of the well-developed binary optical components. Second, compared with other optical multiple-valued number encoding schemes, it reduces the number of input–output channels and thus is able to conserve the optical space–bandwidth product. As an example for arithmetic operations, BCT full addition algorithms are given. As examples for multiple-valued logic computing, BCT Post, Webb, and residue logic elements are discussed. Using the two-port Sagnac interferometric switches, optical implementations of various BCT arithmetic and logic operations are described.

Direct coupled FET logic using a photodiode for biasing or level-shifting

Abstract: A direct coupled FET logic (DCFL) circuit element has an active FET with source connected to a low reference voltage and drain connected through a pull-up FET to a higher reference voltage. An input is applied to the gate of the active FET and the output is taken from its drain, the pull-up FET having its gate connected to its source. In depletion mode configuration, a photodiode is connected to the gate of the active FET, the photodiode energizable to downwardly shift the gate voltage. In enhancement mode configuration, a photodiode is connected between source and gate of the pull-up transistor and is energized to shift the gate voltage upwardly. The photodiodes are integrated with the active and pull-up FETs and are energized by light or decay radiation.

Gate propagation delay and logic timing of GaAs integrated circuits measured by electro-optic sampling

Abstract: We report techniques for measuring internal switching delays of GaAs digital integrated circuits by electro-optic sampling. Circuit propagation delays of 15 ps are measured. A new phase modulation technique which allows testing of sequential logic is demonstrated with the measurement of a 2·7 GHz 8-phase clock generator.

Fabricating a field effect transistor utilizing a dummy gate

Abstract: A process for the fabrication of "low temperature"-gate MESFET structures, i.e., gate metal deposition takes place after annealing of an n + -implant that form source- and drain- contact regions. The process permits self-alignment of all three important MESFET parts, namely, the implanted contact regions, and both, the ohmic, as well as the gate, contact metallizations. In the process, a multi-layer "inverted-T" structure is used as a mask for the n + -implant and for the ohmic and gate metallizations. The upper part of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer of the "inverted-T", the shoulders being obtained using sidewall techniques.

Parallel processing system apparatus

Abstract: Configured for accelerated operation of processing elements in a SIMD parallel processing system is disclosed. The output of an exclusive-OR gate is coupled to one input of the element ALU while a first input of the gate is adapted to receive signals intended for the ALU input. Upon loading a `1` bit into a register coupled to a gate second input, signals applied to the gate first input are complemented and applied to the ALU input. As a result, different arithmetic and logic operations can be performed simultaneously by different elements in the processing system in response to a single series of instructions.

CMOS to ECL converter-buffer

Abstract: The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor. The second terminal of the second transistor is connected to the output terminal and the first terminal of the second transistor is connected to the second power supply terminal. A saturation means is connected between the gate terminal and the second terminal of the second transistor. The saturation means is responsive to the signal on the input terminal for saturating the second transistor in an "ON" state when the logic level 0 is applied to the input terminal.

All-optical, fiber-optic modulator and logic gate using nonlinear refraction and absorption.

Abstract: The first demonstration to our knowledge of new all-optical logic gates and modulators that use nonlinear refraction and absorption to modify fiber-to-fiber coupling is reported. Results are presented for the AND, NOR, NOT, and XOR functions with better than 20-dB contrast ratio. Silicon (at λ = 1.06 μm) is used as the nonlinear material for this proof-of-concept experiment. No resonators, feedback, or stringent wavelength controls are needed. The feasibility of picosecond operation is discussed.

All-fibre-optic logic 'AND' gate

Abstract: Operation of an all-fibre-optic-logic AND gate is demonstrated The logic gate consists of a birefringent fibre, a coiled fibre used as a quarter-wave plate, and a highly birefringent fibre as a polariser The 9 dB extinction ratio of ‘on’ and ‘off’ states is achieved for the all-fibre-type AND gate

CMOS integrated circuit for signal delay

Abstract: A CMOS integrated circuit for signal delay comprises CMOS gate circuits connected in multiple stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element and a P channel element cascade-connected to each other and gate patterns of the respective channels have their width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.

Magnetic recording and reproducing device

Abstract: PURPOSE:To obtain a reproducing output without phase errors and perform recording and reproducing where error bits are not required, by differentiating reproducing signals to generate binary signals according to zero crossing by a two-way monostable circuit and subjecting them to a logical processing. CONSTITUTION:Reproducing signals are applied to differential amplifier 36 and become binary differential signals C different in polarity and are applied to two-way stable circuit 16. Then, two sets of binary signals D and E according to zero crossing of differential signals are generated, and signal E becomes binary signal F shifted together with noise 66 through delay circuit 71 and is applied to latch circuit 72 together with signal D, and binary signal G which is not affected by noise 66 is generated from circuit 76 even if circuit 72 is triggerred by signal E, and this signal E is applied to exclusive OR circuit 77 together with signal D. The output of exclusive OR circuit 77 and signal F are subjected to AND processing by AND gate 74 and become a reproducing output which is not affected by noise, etc., and error bits, etc., are not required. Then, phase delay elements other than circuit 16 do not exist, and so, the phase slippage of the reproducing output is reduced.

Driving method for active matrix type liquid crystal display device

Abstract: PURPOSE: To prevent the generation of uneven luminance by changing over the gate voltage for controlling the on and off of a switching element in such a manner that the data voltage to be impressed to a liquid crystal cell is lower in the value in a frame of a negative polarity than the value in a frame of a positive polarity, thereby driving a titled device. CONSTITUTION: This device is provided with a liquid crystal panel 5 connected with the liquid crystal cell 4 via the switching element 3 such as TFT at the intersected point of a data bus line and gate bus line 2 which are disposed orthogonally with each other. Data is shifted according to a data clock to a data bus driver 6. The data voltage is impressed to the data bus line 1 (D1, D2,...Dm) when the shift for one line ends. Scan data is shifted according to a scan clock to the gate bus driver 7 and the output thereof is impressed as the gate voltage to the gate bus line 2 (G1, G2,...Gn). The polarity of the data voltage to be impressed from the data bus driver 6 to the data bus line 1 is changed over by a change-over signal at every prescribed period such as frame period. COPYRIGHT: (C)1988,JPO&Japio

High speed address transition detector circuit for dynamic read/write memory

Abstract: A transition of an address input of a memory device is detected in a CMOS circuit having a pair of AND gates Or'ed together. One AND gate receives the input bit and a delayed complement of this bit. The other AND gate receives the complement of the input bit and a delayed version of the true bit. The delays are RC circuits with time constants longer than the transition times. The output of the gates uses a pull-up device to restore a zero level after each transition is indicated. A number of these transition detectors may be OR'ed together to monitor all of the address bits of a memory device.

Erasable programmable read only memory (EPROM) device and a process to fabricate thereof

Abstract: A structure of high packing density EPROM having floating gate type FET memory cells and a fabrication process thereof are disclosed. Marginal spaces for mask alignment and bird's beak in prior art EPROM device have been cut down by applying a self alignment technique to determine both the gate length and gate width. The process for fabricating the device is disclosed. On a substrate first gate insulation film and first conductive polysilicon layer are formed. Parallel grooves for device separation are formed in a direction of gate length by photolithography. The space between the groove defines the gate width, and the width of the groove determines the spacing between the cell FETs. The groove is buried by SiO 2 deposited chemical vapor deposition. The surface is etched to expose the first polysilicon layer. On this surface, a second gate insulation film and second conductive polysilicon layer are formed. The substrate is then etched leaving a parallel stripes orthogonal to the device separation grooves. The spacing of the stripe determines the device separation in the direction of gate length. Utilizing this stripes as a mask, the substrate is etched off to expose the substrate. To the exposed substrate are doped to form sources and drains. Applying the inventive process, the packing density of the memory cell has been increased by 30%.

Multiplying interface circuit for level shifting between FET and TTL levels

Abstract: An interface circuit for use as a circuit interface between bipolar ECL logic circuits and field effect transistor circuits. The interface circuit includes an amplifier circuit having an enhancement level shifting and enhancement multiplier device wherein sensitivity to device threshold variations are essentially eliminated. The level shifting portion of the amplifier comprises a load device plus an enhancement type input field effect transistor having a common drain and gate and with its source connected to the incoming ECL level. In dual rail operation, the load device has its gate modulated by the complement of the incoming signal. The output of this stage is the ECL signal shifted upwards by slightly more than the enhancement threshold voltage, making it possible to drive the next multiplier stage without use of any depletion implant. The level shifted signal is applied to the gate of another enhancement device in the multiplier stage, with the complement ECL signal applied to the second enhancement device source electrode. The ECL signal is also used to drive the gate of another load device in the multiplier stage. A drive stage may be added to the combination of the level shifter and multiplier to provide a full output voltage level.

Power structures and logic

Abstract: This paper generalizes the concept of a power alge bra to that of a power structure, and gives three application of power structures to logic.

Pyroelectric type infrared detector

Abstract: PURPOSE: To suppress erroneous output due to popcorn noise, by providing a gate circuit for taking AND of signals outputted from a plurality of respective pyroelectric type infrared detection elements positioned at the emitting region of infrared rays emitted from an article to be detected CONSTITUTION: An element group 11 consisting of pyroelectric type detection elements 11aW11c and an element group 12 consisting of pyroelectric type detection elements 12aW12c are provided in parallel to the moving direction A of a human body 1 and mirrors 4aW4g are arranged in a polygonal array in opposed relation to the elements 11aW11e, 12aW12c Infrared rays emitted from the human body 1 when the human body 1 passes a D-position are incident to the elements 11aW11c through the mirror 4a and signals are outputted from all of the elements 11aW11c and an AND gate 15a is turned ON to output a signal to an alarm through an OR gate 16 Further, when the human body 1 passes a U-position, a signal is also outputted to the alarm through gates 15b, 16 By this method, even when popcorn noise is generated in either one of the element groups 11, 12, the generation of erroneous output can be suppressed COPYRIGHT: (C)1988,JPO&Japio

Automatic gate closure apparatus

Abstract: Gate closure apparatus for closing a gate mounted pivotably on a gate post, such apparatus for connection to the gate and gate post and for developing and storing energy upon opening of the gate, and upon release of the gate, the gate closure apparatus for releasing the energy to produce and apply torque to the gate sufficiently large to close the gate; such apparatus may include a coil spring wound in a predetermined direction and having a normal state, upon the gate opening the spring winding in a predetermined direction out of the normal condition (e.g. coiling further tightly) to develop and store the energy, and upon release of the gate, the spring unwinding and returning to the normal condition to produce and apply the torque to the gate.

Method of making gate turn off switch with anode short and buried base

Abstract: A GTO switch is provided in which the upper base layer (gate) is formed by a diffusion step. An epitaxial layer grown over the upper base layer contains cathode and gate diffusions which are separated by an undiffused gap. This "buried base" technique provides precise control over the resistivity of the base. The cathode-gate gap provides increased reverse gate voltage capacity. Other features include a large anode short area and a double-layer-metal; contact structure on the cathode-gate surface.

Switched capacitor circuit

Abstract: PURPOSE:To prevent overlap of the turn-on state of a clock signal and to operate stably a circuit by providing the switched capacitor circuit with an NOR gate and an AND gate, to which an input clock is applied, an an inverter which inverts the output of the NOR gate and applies in to the AND gate CONSTITUTION:A clock phiIN is applied to one inputs of an NOR gate 1 and an AND gate 3 of a clock generating circuit of the switched capacitor circuit, and the output of the gate 3 is applied to the other input of the gate 1 The output of the gate 1 is inverted by an inverter 2, and an inverted output 12 is inputted to the other input of the gate 3 Outputs of gates 1 and 3 are connected to switched capacitors CA and CB respectively The output of the gate 3 is set to the high level when the clock phiIN is in the high level, and the output of the gate 1 is set to the high level when the clock phiIN is in the low level; and thus, overlap of the turn-on state of the clock signal is prevented to emininate the probability of leakage of electric charge, and the circuit is operated stably

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

Abstract: A theoretical formulation for the hot-electron currents (substrate and gate currents) in MOST's with nonuniform impurity profile has been built By applying a gradual channel approximation for the source section and a pseudo-two-dimensional approximation for the drain section, saturation voltage is obtained by considering the voltage and channel current continuity at the boundary of the two sections Three fitting parameters in the model are determined by comparing the theoretical calculation results with the observed substrate current in samples with various device parameters The present model was successfully applied to describe the two experimental results: the gate oxide thickness dependence of the gate current injection efficiency and the kink in the maximum channel electric field strength versus gate voltage (= drain voltage) relation The nonuniform channel impurity profile is approximated by the modified Gaussian distribution, which is found to agree well with the estimation by the substrate bias effect of MOST's The calculated gate currents for the device can well explain the implantation energy dependence of the measured gate currents

Protecting circuit for field-effect transistor

Abstract: PURPOSE: To absorb surge energy to below the dielectric strength of an FET by connecting a Zener diode and a diode which has the opposite polarity from the Zener diode in series between the drain and gate CONSTITUTION: The series circuit of the Zener diode ZD1 and the diode D1 which has the opposite polarity from the Zener diode is provided between the drain and gate of the N channel FET A voltage applied to the gate G of the diode D1 connected in series between the gate and drain of the FET operates not to be drawn to the drain D and when the FET is off, namely, when a control transistor TR is off, the Zener diode ZD1 feeds the surge energy applied to the FET back to the gate of the FET, thereby reducing the voltage between the drain and gate below a constant value Consequently, the FET consumes the surge voltage and the gate is turned on before a voltage higher than the dielectric strength is applied, thereby lowering the surge voltage COPYRIGHT: (C)1988,JPO&Japio