Showing papers on "AND gate published in 1987"

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.

Programmable array logic cell

Abstract: A programmable array logic cell (60) including a sum-of- products array having a single OR gate (70) for providing a sum signal, and including an XOR gate (80) for combining the sum signal with a product signal provided by an AND gate (78) from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode

Abstract: A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Topological Optimization of Multiple-Level Array Logic

Abstract: A generalized topological optimization tool for array-based layout styles is presented. This tool can be used for automated layout synthesis of logic networks in a variety of technologies and design styles, including static CMOS, static NMOS and dynamic MOS domino structures. Results obtained compare favorably with technology and design-style-specific synthesis systems. The topological optimization tool is a generalized array optimizer which can be used for the multiple constrained folding of programmable logic array, gate matrix, Weinberger array, multilevel matrix, and storage/logic array structures. The optimizer uses simulated-annealing-based algorithms and performs as well as or better than existing specialized PLA folding programs and gate matrix folders. The different layout style alternatives allow area-efficient synthesis of logic circuits in various technologies. Layout for sequential logic in the form of storage/logic arrays has been automated for the first time. A multiprocessor implementation of the simulated-annealing-based algorithms for generalized array optimization has been developed on the Sequent Balance 8000 multiprocessor. Dynamic windowing and dynamic partitioning techniques have resulted in an efficient parallel implementation of simulated annealing.

Statistics for Parallelism and Abstraction Level in Digital Simulation

Abstract: This paper presents statistics of several designs at four design abstraction levels - the instruction, behavioral, RTL, and gate levels. The data includes simulation time profiles, maximum speedup and limitations of parallelism, typical model evaluation times, event distributions, element intensities, and component counts for the four abstraction levels. This data is then used to analyze and evaluate several speed-up approaches: mixed-level simulation, parallel software simulators, parallel pipelined hardware accelerators, and decreased time resolution. The results show that element activity is around 0.1 to 0.5% at any particular time point. For the example circuits (3400 gates, 5000 gates, and 150,000 transistors), simulations show that parallelism can obtain speed-ups between 10-30. We found a factor of roughly ten speed-up between each of the abstraction levels.

Buffered routing element for a user programmable logic device

Abstract: A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

Suspended gate field effect semiconductor pressure transducer device

Abstract: A capacitive pressure transducer comprising: field effect solid state electronic device having a semiconductor gate area, an insulating layer and a gate element; the gate element being made of conducting material and being constructed to move in response to pressure differentials on the two sides thereof so as to function as a diaphragm; the gate element being hermetically sealed along its perimeter with the said insulating layer; the gate element also being a conductor so as to change the capacitance between the said gate element and the semiconductor of said field effect solid state device and cause any change in the output of said solid state electronic device to be a measure of the change of the pressure; and a method of making the suspended diaphragm and gate element.

A high-speed dynamic domino circuit implemented with GaAs MESFETs

Abstract: The dynamic domino and gates composed of GaAs depletion-mode (D-mode) MESFETs are described in this work. This circuit allows very complex input combinational functions which can provide very high gate equivalences. Test circuits were designed which consisted of chains of 15 dynamic AND gates with static off-chip drivers. The circuits were fabricated by a foundry and tested at the wafer level. The measured propagation delay per gate is 180 ps for a two-input AND gate and 220 ps for a four-input AND gate, with a power consumption of 0.55 mW/gate. The minimum frequency of operation is found to be as low as 100 kHz. A 4-b carry generator was designed and simulated. A delay of 400 ps was predicted for this circuit.

Gate operator unit

Abstract: An automatic gate opening device consisting of two arm members pivotally attached to form a link. One end of the link is pivotally attached to one end of a standoff. The second end of the standoff is fixedly attached to a hinge post supporting the gate. The second end of the link is pivotally attached to the gate. An electrically powered linear actuator is pivotally attached to the post arm and gate arm through levers. The solar panel charges a battery which, through a receiver unit, powers the actuator. Gate operator actuates gate with a portable transmitter.

Logic path length reduction using boolean minimization

Abstract: An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

Mechanisms for low-frequency oscillations in GaAs FET's

Abstract: Low-frequency oscillations in GaAs MESFET's were observed under back-gating conditions. The FET oscillations are directly related to oscillations in leakage currents in the semi-insulating GaAs substrate. The occurrence of these oscillations in the substrate is strongly dependent upon GaAs material. It is proposed that oscillating substrate leakage currents modulate the FET current in two ways; first, by modulating the active channel-substrate junction and second, by inducing periodic voltage fluctuations on the gate via gate pad contacts on the semi-insulating substrate. The latter mechanism is dominant and dependent upon gate bias and gate impedance.

The potential of complementary heterostructure FET IC's

Abstract: The performance capability of AlGaAs/GaAs complementary heterostructure FET (C-HFET) integrated circuits has been evaluated in computer simulations. The study is focused on C-HFET designs in which static currents and gate-leakage currents are sufficiently low to take full advantage of the speed, power dissipation, and logic function capabilities of CMOS-like circuitry. ASTAP computer simulations for loaded NAND and NOR circuits are examined over a wide supply-voltage range at both 300 and 77 K in order to determine the potential of various MODFET, MISFET, and SISFET approaches as well as the prospects of future designs. While performance is limited by FET threshold and gate leakage in present C-HFET approaches, the speed of properly designed 0.7-µm C-HFETs at 300 K is projected to be 3 × faster than comparable 300 K Si-CMOS circuits. C-HFET circuits at 77 K are projected to be more than 4 × faster than 77 K Si-CMOS circuits. It is also found that properly designed C-HFET's could operate at speeds close to those of DCFL n-channel HFET circuits while dissipating only 1/10 of the power.

Semiconductor switching circuit

Abstract: of the Disclosure A semiconductor switching circuit comprises an output FET receiving a photovoltaic output generated by a diode array responsive to a light signal from a light emitting element, a depression mode driving FET connected at the drain and source to the gate and source of the output FET, and a constantvoltage conduction element connected in parallel with a resistor connected across the gate and source of the driving FET. The sensitivity of the circuit is elevated by setting the value of this resistor relatively high, whereas the high speed operation can be assured by having discharge current of an accumulated charge across the drain and gate of the output FET bypassed through the resistor.

Domino-type MOS logic gate having an MOS sub-network

Abstract: The invention relates to a logic MOS gate of the domino type, having a precharging transistor, a validation transistor and logic transistors. To prevent unwanted discharging of a precharged high level, which may be induced by at least one input data being stabilized too slowly, that is to say not before a clock signal has risen to the high level, a p-MOS sub-network is arranged in parallel with the source-drain path of the precharging transistor and receives at least the input data which was too slowly stabilized in such a manner as to establish a conductor path which reestablishes the precharged high level.

Analog-to-digital converter error correction circuit

Abstract: An error correction circuit (16) corrects errors in the thermometer code (T 1 -T 7 ) developed by a parallel or "flash" analog-to-digital converter (10). The error correction circuit employs plural similar bit exchange modules (34) of which each includes a 2-input OR gate (46) having common inputs (48 and 50) that constitute the inputs of the bit exchange module. The output (52) of the AND gate and the output (54) of the OR gate constitute the outputs of the bit exchange module. The bit exchange modules receive the digital-to-analog converter thermometer code and are interconnected to correct errors therein resulting from the presence of more than one transition between different logic states for adjacent bits in the thermometer code. The error correction circuit manipulates the thermometer code bits to provide a corrected thermometer code (T 1C -T 7C ) that has only one transition between different logic states for adjacent bits thereof.

Semiconductor integrated circuit device

Abstract: PURPOSE:To enhance the integration of an LSI by multiplexing a plurality of signals by providing a multiplexed signal separating and recovering circuit and a time division multiplexing circuit, and commonly using the input/output pins of the LSI to limit the number of the pins. CONSTITUTION:A multiplexing signal is input from a pin 17 through a signal lie 8 to an input side gate 11. Since '0' level gate signal is input through a gate signal line 10 to the gate 11, the gate 11 is opened, and the signal is input to a multiplexing signal separating and recovering circuit 12. When a select signal is input from a pin 18, one of an AND gate 19a and an inhibit gate 20a is opened, the multiplexing signal is separated, a signal A (or a signal B) is output, and input into an LSI. The outputs from the LSI are multiplexed by a time division multiplexing circuit 15, and output through a gate 14 from the pin 17.

Resonant tunnelling gate field-effect transistor

Abstract: A new negative differential resistance field-effect transistor concept, based on resonant tunnelling, is demonstrated. The gate of this novel device consists of an AlAs/GaAs double barrier. The drain current against drain and gate voltages exhibit a peak due to the quenching of the resonant tunneling gate current. Thus, in addition to negative conductance, this structure exhibits negative transconductance, a uniquie feature in an n-channel device.

Partially enabled programmable logic device

Abstract: A programmable logic device include an AND gate array and an OR gate array, at least one of which is programmable by the user. The AND gate array includes a plurality of input lines, a plurality of product term lines which cross said plurality of input lines, and a plurality of programmable elements located at the intersections between the input and product term lines. An activation control circuit is also provided for activating at least one of the product term lines while keeping those product term lines which are not used for programming deactivated. With this structure, the waste of power can be minimized.

Monolithically integrated optical gate 2 × 2 matrix switch using GaAs/AlGaAs multiple quantum well structure

Abstract: A small-size matrix switch is required for constructing large scale optical switching systems. An optical gate matrix switch, which consists of optical splitters, combiners and gates, is suitable for above requirement because of its potential in regard to short device length and non-blocking and point-to-multipoint connections ability. However, this kind of switch reported so far is a hybrid /1/. In the hybrid type of optical gate matrix switch, it has seemed difficult to interconnect optical gates with optical circuits efficiently and to make a large-scale matrix switch. Therefore, monolithic integration of optical circuits and optical gates is indispensable for a small-size optical gate matrix switch and large-scale optical switching networks.

Warning device for vehicles against an approaching objects

Abstract: A warning device for use on a vehicle for sensing an approaching object when the vehicle is moving backward. The device produces a first signal when the object is in remote proximity of the vehicle and at least a second signal when the object is in close proximity of the vehicle. The device has a circuit for emitting intermittent infrared light when the vehicle is moving backward and a circuit for receiving the infrared light reflected from the object. The circuit for receiving produces a receive signal indicative of the received infrared light. The device further has an output of the circuit for receiving connected to two inverting inputs of both first and second differential amplifiers, inverting inputs of the first and second differential amplifiers being connected by a first and second variable resistors, respectively, to an applied voltage. First and second outputs of the first and second differential amplifiers, respectively, are connected to first and second inputs of an AND gate. An output of the AND gate is connected to a circuit for producing the second signal and the output of the first differential amplifier is connected to a circuit for producing the first signal.

Mosfet with overcurrent protective function

Abstract: PURPOSE: To obtain a MOSFET with a simple structure by a simple manufacturing process by a method wherein the current of a current mirror is detected by the use of the threshold value voltage of a MESFET or JFET, and, in case of abnormality, the gate voltage of the MOSFET in the main current circuit is restricted by the MESFET or JFET. CONSTITUTION: A circuit is provided by a metal gate FET or junction-type FETT 1 ; connected to the first MOSFETM 1 switching a load RL; the second MOSFETM 2 for a current mirror whose number of cells are less than that of the first MOSFETM 1 whose drain and gate are commonly connected to the first MOSFETM 1 ; a current detection resistor Rs connected between the source of the first MOSFETM 1 and the source of the second MOSFETM 2 ; an input resistor R serially connected to the gates of the first and second MOSFETM 1 , M 2 ; whose drain is connected to the gates of the first and second MOSFETM 1 , M 2 ; whose gate is connected to the connection point between the current detection resistor Rs and the source of the second MOSFETM 2 ; whose source is connected to the source of the first MOSFETM 1 . COPYRIGHT: (C)1988,JPO&Japio

Gating Effects on Thyristor Anode Current di/dt

Abstract: Triggering measurements were performed on thyristors with different gate geometries at various combinations of peak gate current, gate pulsewidth, and gate di/dt, to determine the trigger dependence of pulsed anode current di/dt. Peak gate current was varied from 4 A to 12 A, gate pulse width from 250 ns to 8 ?s, and leading edge di/dt from 23 A/?s to 320 A/?s. Only the peak gate current was found to affect pulsed anode current di/dt.

Periodic signal generator circuit

Abstract: In a periodic signal generator circuit, logical threshold values of an inverter for inverting an output signal of a first logical gate circuit (1) and inputting the same to a second logical gate circuit (2) and an inverter (40) for inverting an output signal of the second logical gate circuit (2) and inputting the same to the first logical gate circuit are set low, so that the time when an output signal of one of the logical gate circuits (1, 2) is inverted by inverting an output signal of the other logical gate circuit is delayed. Thus, the periodic signal generator circuit generates a so-called two-phase non-overlapped clock signal.

Distributed channel-bipolar device

Abstract: A merged channel and bipolar device which exploits the distributed character of the device generates useful electronic characteristics by controlling the current and voltage inputs to the four or more terminals attached to the device, said electronic characteristics being useful for affecting the ac and dc current gain of the device, its transconductance, non-linearities, the electronic output characteristics as a function of input signals, electronic switching, gain control, output limiting, heterodyning, harmonic generation and voltage references. Other applications which employ non-linear behavior include distributed amplification of traveling waves, multiple methods for chemical sensing and other sensor applications. The device behavior can be strongly affected by the device's distributed nature with bipolar behavior and FET behavior substantially different in different regions of the device, and the onset and distribution of this heterogenious behavior being affected directly by the input electrical voltages and currents. Channel geometry and conductivity and gate shape (where a gate is employed) can be used to affect the desired electrical performance. Sensing applications can be affected by intentional modification of surface parameters such as surface recombination, velocity, and by choice of gate materials and gate shape where a gate is used. Applications of the device encompass electrical parameter generation useful for circuit applications. An example is the generation of an accurate reference voltage V thg and constant current values, and transducing and sensing applications for sensing chemicals, magnetic fields, forces, pressure, and other tranducing stimuli.

Active load network

Abstract: ACTIVE LOAD NETWORK ABSTRACTAn active load network for a device under test includes a logic circuit for anticipating the out-put state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

Modulation system for evoked response stimulation and method

Abstract: A modulation system used for non-surgical biomedical stimulation and for research in the area of evoked responses and a method thereof is described. The modulation system comprises an AND gate used to gate the interaction of a variable frequency oscillator with the inputs from a manual safety and control switch connected to an inverter which is connected to a third input of the AND gate. A second variable frequency oscillator has a non-inverted output Q. The non-inverted output Q is connected to the second input of the AND gate. The second variable frequency oscillator has an on/off duty cycle. The first variable frequency oscillator has an output which has a pulse repetition waveform. The output of the first variable frequency oscillator is connected to the first input of the AND gate. The pulse repetition waveform of the first variable frequency oscillator has a frequency 100 times greater than the range of the non-inverted output Q frequency. The AND gate has an output connected to the input of a pulse width monostable oscillator. The output of the AND gate is a composite of the pulse repetition waveform and the non-inverted output Q which is connected to the input of a stimulation device such as a CW laser. The method of generating evoke responsive stimulation pulses comprises adjusting the first variable frequency oscillator to obtain a pulse waveform then adjusting the second variable frequency oscillator to obtain a second pulse waveform which generate evoked response stimulation pulses. The evoked response stimulation pulses are then applied to a person.

Multi layer photopolymeric structure for the manufacturing of mesfet devices with submicrometric gate and variable length recessed channel

Abstract: A technique utilizing conventional photolithography to manufacture GaAs MESFET devices having sub-micrometric gate and variable length recessed channel. The structure of these devices consists of two photopolymeric layers separated by a metal interface. The upper, stencil layer sets the aperture of the submicrometric gate. The lower planarizing layer defines the recessed channel, through the metal interface, which acts as a template. The length of such channel may be varied through suitable choice of exposure time of the planarizing photopolymer. By adopting such multilayer structures it is possible to obtain gate lengths of ˜b μm and recessed channel lengths form 0.8 to 3 μm, with a process yield typically better than 90%, simultaneously. Furthermore, by using a thicker planarizing layer in this structure it is possible to obtain a relatively thick metal deposit (typically about 0.8 μm), such as a Ti/Pt/Au overlayer over ohmic contacts and gate pads.

Passive infrared movement receiver

Abstract: The invention relates to a passive infrared movement receiver for switching lighting on and/or off, having an infrared detector (3) and a light-sensitive element (7), an analog/digital converter (6) being connected downstream of the infrared detector (3), possibly via one or more amplifier stages (4, 5), and the light-sensitive element (7) being connected via one or more evaluation stages, which together form a twilight switch arrangement (8) to the input (11) of an AND logic circuit (12), and the analog/digital converter (6) being connected to another input (14) of the AND logic circuit (12), and in the case of which a signal is emitted to the output (15) of the AND logic circuit (12) when a signal is present at both inputs (11, 14). In order to make the infrared movement receiver retriggerable, that is to say sensitive to a plurality of movements of a measurement object taking place at time intervals, an OR logic circuit (16) is connected downstream of the AND logic circuit (12), and a timing element (18) which controls the load switch (21) is connected downstream of the OR logic circuit (16). In this way, the load switch remains closed as long as the infrared detector (3) detects movements of a measurement object, for example a plurality of people entering the response area of the infrared detector (3) successively, even when the light-sensitive element (7) is "seeing" the previously reported "light".

Erasable programmable read only memory using floating gate field effect transistors

Abstract: For an EPROM having floating gate type FET memory cells, required marginal space allowances for mask alignment, and the incidence of bird's beaks, are cut down by applying self alignment techniques to determine both gate width and gate length. On a substrate (1), a first gate insulation film (3) and a first conductive (e.g. polysilicon) layer (PA) are formed. Parallel grooves (11) for device separation are formed in the gate length direction by photolithography. The space between the grooves (11) defines gate width: the width of the grooves determines spacing between the cell FETs. The grooves are buried by insulator (e.g. SiO₂) (12) deposited by chemical vapour deposition. Then etching is used to expose the first conductive layer (PA), and a second gate insulation film (6) and a second conductive (e.g. polysilicon) layer (PB) are formed on the exposed surface. Parallel stripes (7) are formed, by etching the second conductive layer, orthogonal to the grooves (11). The spacing between the stripes determines device separation in the gate length direction. The stripes are then used as the mask for etching to expose the substrate (1) in which sources (9) and drains (10) are then formed by doping

Fast multiplier circuit incorporating parallel arrays of two-bit and three-bit adders

Abstract: A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell includes an AND gate for producing single power product terms by multiplying together one bit from each of the two numbers. These cells are arranged in the arrays such that the total quantity of single power product terms of any particular power in the respective arrays is within 30% of each other. One subset of cells of each array also includes a respective two-bit adder, and another subset of cells of each array includes a respective three-bit adder. These two-bit and three-bit adders are interconnected within each array to form an intermediate result, in parallel with the other arrays, which consists of a partial sum of all product terms in the array together with no more than one remaining carry-in for each bit of that partial sum. All of these intermediate results are then added by parallel input adders to produce the product of the two numbers.