Showing papers on "AND gate published in 1991"

Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Abstract: An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

Logic module with configurable combinational and sequential blocks

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

Self-aligning contact and interconnect structure

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Input/output macrocell for programmable logic device

Abstract: In a programmable logic device having a programmable logic array 15 adapted to receive a plurality of input signals and provide a plurality of output signals (product terms) through an AND logic which depend on the input signals and information stored in the logic array and a macrocell associated with the logic array, the macrocell including a first OR gate group 11 including a plurality of OR gates, each for ORing the predetermined number of the product terms from the logic array; a demultiplexor group 12 including a plurality of demultiplexors each coupled to output of the corresponding OR gate in the first OR gate group 11, each for generating two or more output signals per one input signal; a second OR gate group 13 including a plurality of OR gates each coupled to a corresponding one of outputs of each of the plurality of demultiplexors, each for ORing the corresponding outputs from the plurality of demultiplexors to form a sum data path for the product terms; and an input/output circuit 14 for receiving data from the plurality of sum data paths for the product terms provided by the plurality of OR gates in the second OR gate group 13 to transfer the received data to an output stage or feedback that to the logic array; whereby the plurality of sum data paths for the product terms are provided in one macrocell.

Resonant loop resistive FET mixer

Abstract: A mixer includes a local oscillator (LO) matching network having an LO input port, an RF matching network also having an input port and an IF filter which provides an IF output from the mixer. A FET having a gate, drain and source operates at the center of the mixer. A resonant loop is connected between the drain and gate of the FET. The gate of the FET is connected to an output of the LO matching network. The drain of the FET is connected to an output of the RF matching network. The source of the FET is connected to an input of the IF filter. The resonant loop may incorporate a DC blocking capacitor which does not function as part of the resonant loop, but which serves to block DC allowing the drain and gate of the FET to be biased independently.

Field programmable gate array

Abstract: A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

Zero overhead self-timed iterative logic

Abstract: CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates (1, 2, 3) to be cascaded and pipelined without intervention latches. The inputs (Data In) to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a ''loop'' or ''ring'' of logic which circulates data until the entire computation is complete.

Gate drive for synchronous rectifiers in resonant converters

Abstract: A resonant converter, including a transformer for separating a high-voltage (primary) side from a relatively low-voltage (secondary) side, has at least one synchronous rectifier and an auxiliary sense winding coupled to the gate thereof. The input capacitances of the synchronous rectifiers are reflected to the primary side and the secondary side by the square of the ratio of the number of auxiliary sense winding turns to the number of primary and secondary winding turns, respectively, thereby reducing the required size of the discrete resonant capacitor. In one embodiment, a gate bias voltage approximately equal to the device threshold voltage is applied to the gate of the synchronous rectifiers. The auxiliary sense windings are etched into a conductive film pattern of the secondary windings. The auxiliary sense windings provide nearly identical secondary and gate drive voltages so that the synchronous rectifiers are gated substantially at the zero-voltage crossings of the secondary winding voltages. The result is a substantially lossless gate drive for synchronous rectifiers in high power density resonant converters.

Semiconductor integrated circuit device

Abstract: PURPOSE:To protect power supply and internal elements from breakdown or damage and to enable quick and efficient current supply by providing a power supply protective circuit for a logic circuit section where the collector and the gate of an isolated gate bipolar transistor having a gate isolation film substantially as thick as an MOS transistor are connected with power supply wiring and the emitter thereof is connected with ground wiring. CONSTITUTION:Collector electrode 72 and gate electrode 73 of an isolated gate bipolar transistor (IGBT 7) having a gate oxide film 74 substantially as thick as a high breakdown strength MOS transistor are connected with power supply winding VDD and the emitter electrode 71 thereof is connected with ground winding VSS, thus forming a power supply protective circuit for a logic circuit section.

Convertible multi-function microelectronic logic gate structure and method of fabricating the same

Abstract: A plurality of field effect transistors (FETS) (Q 0 A to Q n-1 A, and Q 0 B to Q n-1 B) are arranged in a structure (10) to normally perform a first logic function such as NAND. Selectively implanting the channel region (38) of at least one of the FETs (30) with sufficient ions of a predetermined ion species such that the respective FET (30) maintains a constant logic state (constantly turned ON or OFF) for all logical values of applied gate voltage converts the structure (10) to perform a second logic function such as NOR. Alternatively, one of the logic states may be "stuck high" (constant logical high output) or "stuck low" (constant logical low output). The channel implants are substantially undetectable, rendering the structure (10) highly resistant to reverse engineering.

On the modeling and testing of gate oxide shorts in CMOS logic gates

Abstract: The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be dependent not only on inputs to the gate containing the fault but also on other signals in the circuit, and can escape tests generated using normal TPG schemes. The stuck-at test set for a logic gate cannot guarantee to detect all transistor gate-to-source and gate-to-drain shorts in the logic gate. Gate oxide shorts in n-channel transistors affect circuit operation more severely than those in p-channel transistors do. Some limitations of present transistor-level fault modeling techniques are revealed. >

Cascadable surface-emitting laser logic: demonstration of Boolean logic

Abstract: The authors demonstrate cascadable optical logic (AND-, OR- and exclusive OR-gates) implemented with heterojunction phototransistors and vertical-cavity surface-emitting lasers. They also discuss an architecture for implementing binary arithmetic using cascadable surface-emitting laser logic devices and optical symbolic substitution.

Flexible graphics interface device switch selectable big and little endian modes, systems and methods

Abstract: A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the nth first AND gate 126 coupled to the nth one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an nth one of the second AND gates 128 coupled to a (j-n+1)th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an mth one of the OR gates 130 being coupled to the output of an mth one of the first AND gate 126, the second input port of an nth one of the OR gates 130 coupled to the output of the nth one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j.

Manufacture of semiconductor device

Abstract: PURPOSE:To execute the whole process at a low temperature and to execute a high-accuracy processing operation by a method wherein a plurality of gate oxide films having two or more kinds of film thicknesses are formed on a semiconductor substrate and gate electrodes of two or more kinds of conductivity types are formed on the individual films. CONSTITUTION:An element isolation and insulating film 2 is formed selectively on the surface of a semiconductor substrate 1. After that, an oxide film 8 which is used as one part of a first gate oxide film is formed; after that, its one part is removed. Then, a second gate oxide film 5 having a film thickness of 30nm is formed; at this time, the first gate oxide film 3 becomes 38nm. Then, boron ions 7 used to control a threshold voltage are implanted; a polysilicon thin film is formed. In succession, an element formation region corresponding to the film 5 is covered with a first resist 9; boron 10 is ion-implanted. Then, an element formation region corresponding to the film 3 is covered with a second resist 11; arsenic ions 12 are implanted. A first gate electrode 4 and a second gate electrode 6 are formed. Thereby, the whole process is executed at a low temperature, and a high-accuracy processing operation can be executed.

Thin film transistor having an improved gate structure and gate coverage by the gate dielectric

Abstract: A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.

Logic synthesis of 100-percent testable logic networks

Abstract: An approach is presented for the synthesis of 100% testable logic networks based on a test pattern generation system for the identification of redundant faults. A redundancy removal procedure for the elimination of redundant nodes and gates from the network is also presented. Elimination of redundancy is an important task in a logic synthesis system that aims at the synthesis of 100% testable logic networks. Logic synthesis algorithms tend to generate a large number of redundancies, most of which can be easily identified, but some of these redundancies are very hard to identify by logic minimization procedures as well as by conventional test pattern generation algorithms. >

Method for fabricating memory cell matrix having parallel source and drain interconnection metal lines formed on the substrate and topped by orthogonally oriented gate interconnection parallel metal lines

Abstract: A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells. In ROM devices, the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes. The fabrication process employs self-alignment techniques and masks with a relatively low alignment criticality.

Pullup resistance control input circuit and output circuit

Abstract: In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P i ) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q 1 ) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q 1 ) has a drain and a source which are connected to the input terminal (P i ) and a power source (V DD ) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P i ). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P i ) has been at a low logical level, the pullup transistor (Q 1 ) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To achieve higher integration of elements by forming gate electrodes in trench grooves for island type active regions and causing the side part of the active region to be a channel region. CONSTITUTION:A plurality of island type active regions P1-P3 separated by dielectric isolation films and insulating films 30 are juxtaposed on a p-type silicon substrate 21. A drain wiring electrode 31 is continuously formed above these regions P1-P3, and gate electrodes 29 are formed between the regions P1-P3. Drain regions 26 are formed on the regions P1-P3 under the electrode 31, and gate oxide films 28 are formed on the side surfaces of the electrode 29. Source regions 25 are formed under the electrodes 29 via field oxide films 27, and are sandwiched by gate insulating films 30 and buried in trench grooves. Then, gate electrodes are formed in the trench grooves and the side surfaces of the regions P1-P3 are caused to be channel regions so that higher integration can be achieved.

Spike filtering circuit for logic signals

Abstract: A spike filtering circuit for a logic signal comprises a signal transfer circuit formed by a first transfer gate followed by a pair of inverters, functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate connected between the output terminal and the input node of the first of said two inverters. The two transfer gates are driven in phase opposition to each other by means of a pair of control signals in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate having two inputs connected to the output terminal of the circuit directly and through a delay network, respectively. Through an output node of the exclusive-OR gate is produced a first control signal from which the pair of control signals in phase opposition to each other are derived by means of inverting stages. The delay network introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate is momentarily disabled and said second transfer gate is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may be been generated by said transition of the logic signal. By employing a NAND gate and an inverter connected in cascade to the output of said exclusive-OR gate, the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

Integrated high speed synchronous counter with asynchronous read-out

Abstract: Disclosed is a high speed, synchronous counter (102) which counts using a Gray code. Because Gray code counting has the unique property that only a single bit of the counter changes with each new count, the output of the counter (102) may be latched at any time and the latched value will never be more than one count away from the actual count value in the counter. The present invention provides a look-ahead qualification bit (240) that provides for an eight count look-ahead. With this eight count look-ahead capability, the qualification inputs to the high order bits can be created through a series of AND gates (418, 420, 422, 424), each having only two inputs, thus saving significant power and space. Because most digital circuits require the output of a counter to be in binary code, the invention provides a conversion means (106) for converting the Gray code output to a binary output.

Soft error protection using asymmetric response latches

Abstract: A static latch design is analyzed whose single event upset (SEU) sensitivity is extremely dependent on its logic state. The authors employ a modification of a hardened static memory cell to construct an asymmetrical latch. Both the original and asymmetric latches are illustrated. The original idea was that resistors in the drain lines provide voltage division at the feedback point for p-drain strikes (or voltage transients). Proper choice of the resistor value relative to the on resistance of the n-channel transistor will insure that the feedback voltage can never reach the switch point of the opposite inverter, preventing cell upset for any p-drain transient. Such latches respond symmetrically with respect to logic state, displaying essential immunity to one SEU mechanism. A simple AND gate for two of these asymmetric response latches provides high-speed error correction for a single bit, and the combination represents a hardened logic element. >

Multiplexer for use in a full adder having different gate delays

Abstract: The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node The first and second gates turn on complementarily to each other The first gate has an output load capacitance viewed from the output node less than that of the second gate The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level The second gate receives, as the second signal, a signal to be transmitted at a high speed Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed

High electron mobility transistor

Abstract: A high-electron mobility transistor or HEMT has a top surface layer (22) between its gate and drain arranged to produce a channel to drain conductance that is close to the ungated channel conductance to lower the output conductance and reduce gate leakage and gate capacitance. The transistor has high band-gap active layer (20) to produce a 2DEG channel (16) in an adjacent layer, and source (38), gate (34) and drain (40) electrodes on the active layer. An undoped or lightly doped surface layer (22) in the region between the gate and the drain produces a low conductance for a region of a few hundred A from the drain-side edge of the gate. This spreads the electric field domain over at least this few hundred A distance.

High frequency JFET

Abstract: The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The charge of the implanted ions is the same as the charge polarity of the gate regions. To improve the overdrive capability of a JFET a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region i.e., the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region. The second junction in the gate region of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to prior art JFETs. A new method is used to form a guard ring surrounding the active area of a JFET. The JFET formed using this method has a guard ring of a second conductivity type extending a first distance D1 into a layer having a first conductivity type and a gate region of the second conductivity type extending a second distance D2 into the layer. The method of this invention allows selection of the first and second distances D1, D2 to optimize the breakdown voltage and performance of the JFET of this invention.

Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors

Abstract: A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Read only memory device with high speed data output unit

Abstract: A read only memory device comprises a memory cell array, a selector unit interconnecting one of the memory cells to an input node of a sense amplifier unit for producing a read-out signal at a read-out node, a reference unit for producing a reference signal with an intermediate voltage level between voltage levels corresponding to logic "1" bit and logic "0" bit, and a voltage comparator coupled to the sense amplifier unit and the reference unit, wherein the sense amplifier unit has a load transistor continuously supplying current to the read-out node, a transfer gate transistor for interconnecting the input node and the read-out node under the control of an inverting amplifier coupled to the input node, and a charging transistor for providing an auxiliary current path to the read-out node upon rapid decay in voltage level at the read-out node, thereby causing the read-out signal to quickly become stable.

Image filter circuit

Abstract: PURPOSE:To realize simple and high-speed processing by constituting an image filter by inputting image data to a shift register, and logical-operating an image element interposed between under-mentioned two points according to the state of the specified two points of the data in a shifting process CONSTITUTION:In this example, the white run of the run length below an integer (n) latched in a register 1 is eliminated The image data inputted serially from an input terminal 19 is outputted through FFs 4 to 7 and OR gates 8 to 10 The bit pattern of three bits shown in a separate figure is generated by a mask generation circuit 3 according to the value of (n) latched in the register 1 By applying logic between this bit pattern and the output three bits of the gates 8 to 10 by logic gates 11 to 15, the logic whether the white run length of the image data in the shift register constituted of the FFs 4 to 7 is shorter than the integer (n) latched in the register 1 or not is outputted to the output side of an AND gate 15 When the white run length is shorter than the integer (n) latched in the register 1, filter processing is executed

Driver circuit for in-circuit overdrive/functional tester

Abstract: A driver circuit for use in a circuit board tester which tester can perform both functional and in-circuit tests on a given device under test (DUT). The tester provides a test signal representative of a command for the driver circuit to provide logic high or logic low signals to a given device under test (DUT). The driver includes an output stage for providing desired logic high and logic low signals in response to the test signal; and switch circuitry, connected between the tester and the output stage, for preventing the test signal from reaching the output stage in response to a second control signal. The driver circuit is also shown to include an amplifier which, during operation of the driver circuit, receives feedback from the output stage. In addition, the driver circuit includes another output stage which provides a feedback signal when the driver circuit is in tri-state (deactivated). The driver circuit provides a low output impedance when logic high and logic low signals are being provided and a high output impedance when the driver circuit is in tri-state.

Single level bipolar ECL flip flop

Abstract: An ECL OR gate circuit, or a logical equivalent AND gate circuit, is provided whereby the input signals are both referenced to the same bias reference signal such that the propagation delay between each input port to the output port of the gate is substantially equivalent. Also provided is an improved ECL flip flop circuit using the ECL OR (or AND) circuit taught in accordance with the teachings of this invention for a faster ECL flip flop. In accordance with the teachings of this invention, a flip flop clock input signal is referenced to the same bias reference signal as the flip flop data input signal such that the propagation delay between the clock input to the output stage is substantially the same as the data input to the output stage.