Showing papers on "AND gate published in 1992"

Logic cell for field programmable gate array having optional internal feedback and optional cascade

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Automatic gate-level synthesis of speed-independent circuits

Abstract: A CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates is presented. The synthesized circuits are speed-independent-that is, they work correctly regardless of individual gate delays. Synthesis results for a variety of specifications taken from industry and previously published examples are presented. The speed-independent circuits are compared with those non-speed-independent circuits synthesized using previously described algorithms, in which delay elements are added to remove circuit hazards. These synthesis results show that the new circuits are on average approximately 25% faster with an area penalty of only 15%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints. >

Apparatus for insuring the security of output signals from protective relays used in electric power systems

Abstract: In a protective relay (10), which contains a microprocessor (30), for monitoring a power transmission line, an output enable decoder (72) and a one-shot timer (74) produce a very short (5 microsecond) signal in response to an address signal from the microprocessor. The output from the timer is applied as one input to AND gate (70). A conventional address decoder, responsive to an address signal identifying a particular output port from the microprocessor, provides another output to AND gate (70). AND gate (70) produces a latch control signal when the two signals are coincident in time. The latch control signal enables the particular output port to receive instructions from a data bus (60).

Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions

Abstract: The input/output circuit cells of a master-slice gate array device have the same diffusion and gate regions as the basic transistors so that the input/output of the device may be defined at the metallization stage rather than at the time the diffusion regions are formed. Thus a single size master-slice circuit device need to be kept in inventory. The array size is selected in accordance with the customer's specification and the inputs/outputs are defined accordingly using CAD. Thereafter, the die may be scribed into smaller. The transistors for sea-of-gate structures containing a pair of long channel transistors whose drain, gate and source regions lie on a single grid or track of the CAD design tool. By using a long channel transistor in the feedback loop of a memory cell, gating transistors may be eliminated to reduce transistors required for latches. To provide the required drive capability, a number of transistors may be connected to form the input or output buffer, without requiring large transistors with large diffusion regions. A metal silicide resistor and a number of discharge transistors normally in the off condition are connected to the node between an input/output pad and input/output buffer for electrostatic discharge.

Automatic gate-level synthesis of speed-independent circuits

Abstract: In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speedindependent circuits synthesized using the algorithms described in [I], in which delay elements are added to remove circuit hazardr. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only IS%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efJrcient circuits compared to those synthesized with timing constraints.

A resonant pulse gate drive for high frequency applications

Abstract: The analysis and implementation of a resonant pulse gate drive are discussed. The resonant gate drive is based on a simple charge pulse circuit which has conduction and logic losses. The pulse charging and discharging instances are controlled by the user, and hence this circuit is applicable to pulse width modulation (PWM) schemes as well as resonant converters. Theoretical analysis of the circuit shows its operation. Detailed equations are presented which describe the inherent losses of the circuit. Experimental results are shown to verify the operation and loss mechanisms. >

Method of making a power VFET device using a p+ carbon doped gate layer

Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

High-breakdown-voltage MESFET with a low-temperature-grown GaAs passivation layer and overlapping gate structure

Abstract: GaAs MESFETs were fabricated using a low-temperature-grown (LTG) high-resistivity GaAs layer to passivate the doped channel between the gate and source and between the gate and the drain. The gate was fabricated such that the source and drain edges of the metal gate overlapped the LTG GaAs passivation layer. The electric fields at the edges of the gate were reduced by this special combination of LTG GaAs passivation and gate geometry, resulting in a gate-drain breakdown voltage of 42 V. This value is over 60% higher than that of similar MESFETs fabricated without the gate overlap. >

Canonical signed two's complement constant multiplier compiler

Abstract: A constant multiplier compiler model allows a modified canonical signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a modified canonical signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. The number of zeros in the multi-bit constant is first maximized by converting the constant to modified canonical form. Then, for each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.

Pulse synchronizing circuit

Abstract: PURPOSE:To prevent the occurrence of contention resulting in causing uncertain timing even when an input pulse and a clock pulse are asynchronous by providing a function to discriminate the contention between the input pulse and the clock pulse. CONSTITUTION:An output (b) of a pulse width shaping circuit 31 and an output (c) of a delay circuit 32 are inputted to a discrimination circuit 33, in which whether or not leading edges of the pulse outputs b, c are close to each other, that is, the relation of contention is discriminated. The output (b) of the pulse width shaping circuit 31 and the delay output (c) of the delay circuit 32 are latched respectively by DFFs 331, 332 by using a 2nd clock CK 2. Then an output (d) of the FF 331 and an output (e) of the FF 332 are decoded by an inverter 333 and an AND gate circuit 334. After the decoding, an output of the gate 334 is latched at a trailing edge of the delay pulse (c) to output an output (f) for discriminating the contention.

Ultrafast soliton-trapping AND gate

Abstract: An ultrafast, all-optical, soliton-trapping AND gate that consists of a birefringent optical fiber followed by a frequency filter is demonstrated. The gate is sensitive to the timing of the input pulses and provides an output with a large energy contrast. The performance of the gate is characterized by varying the total input energy, the ratio between the energies of the two input pulses, and the arrival-time difference between the input pulses. It is shown that the gate efficiency (characterized by its ON-OFF contrast ratio) increases with increasing pulse energy up to the limit where Raman effects become dominant in the fiber, and the optimal performance of the gate is obtained with two input solitons having equal energies. The gate efficiency degrades with increasing difference of arrival time of the two input pulses, but a contrast ratio of 5:1 can still be obtained for a full pulse width of timing mismatch. The experimental results are in agreement with numerical simulations using the coupled nonlinear Schrodinger equations. >

Method for disguising a microelectronic integrated digital logic

Abstract: Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

Abstract: Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

High performance architecture for image processing

Abstract: The logical computer architecture is specifically designed for image processing, and other related computations. The architecture is a data flow concept comprising three tightly coupled components: a spatial configuration processor, a point-wise operation processor, and a accumulation operation processor. The data flow and image processing operations are directed by the control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of pixels in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms, including a hybrid electro-optical implementation, and an all digital implementation. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra's generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.

Hybrid manufacture of air gap and gate of Suspended Gate FET without using spacers producing gate separately from base structure, with air gap height based on height difference of channel and field isolators

Abstract: The method is performed without adding material which must be subsequential removed. The air gap is formed by a gate produced separately from the production of the FET base structure. A chemically sensitive surface can be optionally added to the gate which is applied to the base structure as a hybrid with an air gap height resulting from the height difference between the channel (6) and field (3) isolators. USE/ADVANTAGE - For producing SGFET with freely accessible space between gate electrode and channel isolator, e.g. for use in ion concentration analysers. High purity and low surface roughness can be achieved.

Neuron unit and neuron unit network

Abstract: A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving first and second input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the first input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the second input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.

Layout comparison of MOSFETs with large W/L ratios

Abstract: Theory is developed on the layout of MOSFETs with large W/L ratios. Different layout styles are also compared for the performance criteria such as area, gate capacitance, drain (source) capacitances and gate resistances. The waffle iron layout style is superior to conventional finger layout in terms of area and gate resistance, whereas finger layout has lower gate capacitance.

Energy minimization based delay testing

Abstract: The authors present a novel method for generating robust and non-robust tests for path or gate delay faults in scan and hold type of sequential circuits. The relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function such that minimum-energy states correspond to signal values that are consistent with the gate logic function for both input vectors. The energy function for the circuit is the summation of individual gate energy functions. It implicitly contains information about hazards. For a given delay fault, the energy function is suitably modified so that minimum-energy states are guaranteed to be hazard-free or robust delay tests. Results on sequential benchmark circuit are given. >

Fuzzy controller on FPGA chip

Abstract: A hardware implementation of fuzzy controllers on field programmable gate arrays (FPGAs) is described. FPGAs are semicustom integrated circuits that combine the attractive features of both programmable logic devices and gate arrays. Software for synthesizing fuzzy controllers into Boolean equations was developed. The file that contains the set of Boolean equations is accepted directly by the development system of the FPGA. The development system then produces the necessary code for programming the FPGA chip. The speed of the fuzzy controller is determined by the response time of the FPGA circuit that realizes the Boolean equations. A speed of 50M FLIPS was achieved. The software together with the FPGA development system provide a complete design automation tool for fuzzy controllers. >

High stability static memory device having metal-oxide semiconductor field-effect transistors

Abstract: A static memory device has memory cells each having a pair of driver MOSFETs, two load resistors each connected between a power source and a drain of each of the driver MOSFETs, two access MOSFETs each of which is connected between the drain of each of the driver MOSFETs and each of bit lines and gates of which are connected to a word line. In the memory cell, the thickness of a gate oxide film of the access MOSFET is made thicker than that of the gate oxide film of the driver MOSFET. The operation stability of the memory cell is enhanced, without the need of increasing a chip size, by increasing a ratio between the driver MOSFETs and the access MOSFETs of the memory cell (the ratio of current supplying capabilities of the two transistors) without making a gate size large or without making it so small as to cause process variations.

Insulated gate type semiconductor device

Abstract: PURPOSE:To achieve an insulated-gate type semiconductor device that requires a low gate driving energy and induces a low switching loss at a low ON-state voltage by the use of a current absorbing means disposed on an epitaxial layer by way of an insulation film CONSTITUTION:A gate terminal 12 connected with a first gate electrode 6 is connected to an output terminal of a normal gate driving circuit 19, and a second gate terminal 14 connected with a second gate electrode 7 is connected to a positive potential side of a driving circuit power supply 18 The second gate electrode 7 is therefore connected to a source electrode 9 in the manner of an alternating current The majority of a potential current occurring at the time of switching is bypassed to the source electrode 9 in a regulated manner, and hence it becomes possible to suppress a displacement current that flows through the gate electrode 6 Therefore, variations in a voltage between the gate and the source are not hindered, and gate displacements vary in a short period, whereby it is possible for an element to achieve a low driving energy and a low switching loss

Common edge output skew detection circuit

Abstract: An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n outputs. The output skew detection circuit senses common edge output skew across the n in phase output signals simultaneously and directly. A first logic gate has n inputs coupled to the n outputs, detects occurrence of either the first or last of the multiple common edge output signals, and generates a first skew detection edge signal at a first logic gate output. The first and last common edge output signals are the signals propagated with minimum and maximum propagation times tplhmin, tphlmin and tplhmax, tphlmax. A second logic gate has n inputs coupled to the n outputs in parallel with the first logic gate. The second logic gate detects occurrence of the other of the first and last of the multiple common edge output signals and generates a second skew detection edge signal at a second logic gate output. The respective inputs of a third logic gate are coupled to the first and second logic gate outputs. The third logic gate generates a pulse signal having a pulse width or pulse duration determined by the first and second skew detection edge signals at the inputs of the third logic gate for providing a pulse width measure of the maximum output skew tOSLH, tOSHL between the first and last of the multiple common edge output signals. A pulse width detection circuit such as a flip flop coupled to the third logic gate delivers a threshold flag signal upon occurrence of a pulse signal having a pulse width greater than a specified pulse width threshold value corresponding to a maximum permitted output skew.

Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects

Abstract: Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate level test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.

Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers

Abstract: The authors present a concurrent fault simulation algorithm. The pipelined algorithm is suitable for implementation on memory limited hardware accelerators and message passing multicomputers or specialized hardware. The architecture of the system and the data structures and algorithms for some of the crucial parts of the fault simulation algorithm are outlined. For pipelined architectures, fault simulation is illustrated for circuits modeled at mixed functional and gate levels. The results indicate an order of magnitude speed up compared to a production quality simulator running on a SUN SPARC2. >

Divider circuit structure

Abstract: A divider circuit provides an output signal having a frequency which is equal to the frequency of an input signal divided by an odd integer. This is achieved by feeding back the output from a binary counter through an AND gate, delay flip-flop and an OR gate so that one cycle is added the output of the binary counter.

Programmable logic device

Abstract: A programmable logic device includes groups of AND logic function gates, the AND logic function gates in each group coupled to a logic OR function output gate associated with that AND logic function gate group. Each AND logic function gate group includes an output AND logic function gate having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that output AND logic function gate. The PLFGs in any set of PLFGs receive the same sets of first logic input groups, and second programmable inputs. Operation of Boolean function generator output stages to carry out logic operations is controlled by first inputs from the logic OR function gates, and second programmable inputs received from logic cells according to logic inputs to said programmable cells. Inputs from the logic OR function gates are selected by programmable OR logic function generators. The PLFGs and BLFGs comprisise logic circuitry to generate output signals determined by any logic function of a plurality of the first logic inputs, and the second inputs. Using this PLD structure, outputs from the PLD can be used to control logic operations performed by the BLFGs using logic values and instructions originating externally of the PLD.

Initializability Consideration in Sequential Machine Synthesis

Abstract: It is shown that a finite state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable (i.e., has synchronizing sequences). A fault simulator or a sequential circuit test generator, that assumes all memory elements initially to be in the unknown state, will be totally ineffective for such a design. Proper consideration for initializability during state assignment and logic optimization can guarantee the success for gate level analysis tools. In this paper, the conditions for initializability of finite state machines are derived and an automatic state assignment algorithm for logic minimality and initializability is given. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique, recommended for machines without a synchronizing sequence, is also discussed.

Thin film transistor having an inverted stagger type structure

Abstract: A thin film transistor having an inverted stagger type structure is formed on a substrate. A gate film having a gate electrode portion is formed on the substrate. A gate insulating film is formed on the gate electrode portion of the gate film such that the gate insulating film is located entirely inside a perimeter defied by the outer edges of the gate electrode portion. A polycrystalline semiconductor film, which is an active layer of the transistor, is formed on the gate insulating film such that it is entirely inside a perimeter defined by the outer edges of the gate insulating layer. The polycrystalline semiconductor film, gate insulating film and gate film are selectively photoetched after being formed on the substrate. Source and drain electrode films are formed so that the electrode films electrically connect with the polycrystalline semiconductor film.