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Showing papers on "AND gate published in 1993"


Journal ArticleDOI
01 Jul 1993-Nature
TL;DR: A receptor is described that operates as a logic device with two input channels: the fluorescence signal depends on whether the molecule binds hydrogen ions, sodium ions or both and the input/output characteristics of this molecular device correspond to those of an AND gate.
Abstract: MOLECULES that perform logic operations are prerequisites for molecular information processing and computation1–11. We12,13 and others14–16 have previously reported receptor molecules that can be considered to perform simple logic operations by coupling ionic bonding or more complex molecular-recognition processes with photonic (fluorescence) signals: in these systems, chemical binding (the 'input') results in a change in fluorescence intensity (the 'output') from the receptor. Here we describe a receptor (molecule (1) in Fig. 1) that operates as a logic device with two input channels: the fluorescence signal depends on whether the molecule binds hydrogen ions, sodium ions or both. The input/output characteristics of this molecular device correspond to those of an AND gate.

1,059 citations


Patent
01 Apr 1993
TL;DR: A TFT array has a plurality of gate lines and drain lines formed on a transparent insulating substrate The gate lines intersect with the drain lines TFTs are formed at the intersections of the gate line and the drain line.
Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate The gate lines intersect with the drain lines TFTs are formed at the intersections of the gate lines and the drain lines An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images

139 citations


Patent
30 Mar 1993
TL;DR: In this paper, a three-dimensional multichannel structure of a thin-film transistor gate with a 3D multi-channel structure is described, where the source/drain electrodes are formed so as to be spaced from and opposite to each other on a substrate, and the whole outer layer of each sub-semiconductive layer is used as channel regions.
Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

116 citations


Journal ArticleDOI
Jonathan W. Greene, E. Hamdy1, S. Beal1
01 Jul 1993
TL;DR: A brief survey of antifuse technologies is provided in this paper, where the tradeoffs involving the antifuses characteristics, routing architecture and logic module are illustrated, as well as some inherent tradeoff involving the Antifuse characteristics and routing architecture are illustrated.
Abstract: An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated. >

98 citations


Patent
10 Dec 1993
TL;DR: In this paper, a logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals.
Abstract: A logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals. First and second input terminals (a, b) are connected to inputs of a first XOR gate (22); a third input terminal (c) is connected to one input of a multiplexor (24) through an inverter (26); a fourth input terminal (d) is connected to the other input of the multiplexor (24) and to one input of a first NAND gate (28); and a fifth input terminal (e) is connected to one input of a second XOR gate (30) and to one input of a second NAND gate (32). The first XOR gate (22) has its output connected to the other input of the first NAND gate (28) and to the control input of the multiplexor (24). The output of the multiplexor (24) is connected to the other inputs of the second XOR gate (30) and second NAND gate (32). The outputs of the first and second NAND gates (28, 32) are connected to the inputs of a third NAND gate (36). The outputs of the third NAND gate (36) and second XOR gate (30) are the output terminals (F2, F1) of the logic module (10). The configuration of the logic module (20) permits implementation of adders and subtractors for DSPs with only one logic module.

63 citations


Patent
Michael R. May1
27 Dec 1993
TL;DR: In this article, a voltage controlled oscillator (VCO) includes a periodic signal generator (30), a comparator (42) followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch to adjust for asymmetries in the output signals from the latch.
Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

62 citations


Patent
23 Mar 1993
TL;DR: In this article, an image-recorder chip having a multiplicity of image cells provided with field effect transistors disposed in the form of a two dimensional array and having a readout logic is presented.
Abstract: Disclosed is an image-recorder chip having a multiplicity of image cells provided with field-effect transistors disposed in the form of a two dimensional array and having a readout logic. This present invention is directed to the object of projection of high input signal dynamics onto reduced output signal dynamics, and is distinguished by the arrangement of the light-sensitive element of each image cell being connected between one electrode of a first MOS transistor and gate of a second MOS transistor, and by the other electrode of the first MOS transistor being connected to the one pole of a voltage supply source.

56 citations


Patent
30 Apr 1993
TL;DR: In this paper, a field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed.
Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.

47 citations


Journal ArticleDOI
TL;DR: A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented, targeted at circuits with highly connected state transition graphs as in data paths.
Abstract: The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. The approach is targeted at circuits with highly connected state transition graphs (STGs) as in data paths, but explicit use is not made of the STG. The efficacy of the method stems from the use of the RTL description and good heuristics. The authors have successfully generated tests for entire chips with large numbers of latches within reasonable amounts of CPU time and have obtained maximum fault coverage. The algorithms require significantly smaller times than other test generators. A synthesis procedure that produces an optimized, fully testable logic implementation of a sequential circuit from a RTL description of the sequential circuit is also described. Datapath-controller circuits as well as digital signal processors whose STGs are very large, can be synthesized. The problem of synthesis of sequential logic for testability is also addressed. >

45 citations


Proceedings ArticleDOI
09 May 1993
TL;DR: Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs.
Abstract: The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA.

43 citations


Patent
03 Mar 1993
TL;DR: In this paper, a feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enabling gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off.
Abstract: DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from output buffer logic utilized in reading data out of the DRAM. Output signals from the level translator stage are applied to a pull up output transistor in an output driver stage, and output signals from the enable gate are connected to a pull down output transistor in the output driver stage. A feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enable gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off. Not only does this novel operation completely eliminate crossing or crossover currents in the output driver stage, but it also introduces minimum time delays in logic swings at the output node of the output driver stage.

Patent
John E. Gersbach1, Ilya I. Novof1
26 Mar 1993
TL;DR: In this paper, a digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter, which is responsive to a first set of control signals received from the up and down counter to provide an output signal.
Abstract: A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto The decoder provides a separate output line for each of the delay elements which is to be selectively activated The logic required to implement the decoder requires only a single AND gate and a single OR gate for each of the delay elements in the array

Patent
07 Jan 1993
TL;DR: In this paper, a solid state image pickup device is composed of basic cells each of which comprises a photodiode one terminal of which is grounded, a n-MOS transistor whose gate is connected to the other terminal of the photode and whose source is grounded and furthermore, a feedback capacitor and switching element for resetting both of which are connected between the drain and gate of the n-mOS transistor.
Abstract: A solid state image pickup device is composed of basic cells each of which comprises a photodiode one terminal of which is grounded, a n-MOS transistor whose gate is connected to the other terminal of the photodiode and whose source is grounded and furthermore whose drain is connected to a load, a feedback capacitor and switching element for resetting both of which are connected between the drain and gate of the n-MOS transistor. As an advantage of such a configuration, the reduction of the sensitivity due to the junction capacitance of the photodiode can be suppressed, and furthermore accurate signal output voltages can be obtained even in the case where the amount of incident light changes during an integration period.

Patent
Jumpei Kumagai1, Tomohisa Mizuno1
15 Sep 1993
TL;DR: In this article, a gate electrode is formed on the gate insulating film and a gate wall is constructed on the sides of the gate and gate electrode, extending upward from the substrate.
Abstract: At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

Patent
01 Feb 1993
TL;DR: In this paper, a valve for rapidly switching high voltage at high currents includes several identical modules series-coupled between the high voltage rails, each module includes a three-terminal semiconductor voltage controlled gate turn-off device ("VCGTO"), an input port for receiving a preferably coupled gate drive signal, input circuitry, two power switching ports coupled to the VCGTO device output terminals, and an output circuit coupled across the output terminals.
Abstract: A valve for rapidly switching high voltage at high currents includes several identical modules series-coupled between the high voltage rails. Each module includes a three-terminal semiconductor voltage controlled gate turn-off device ("VCGTO"), an input port for receiving a preferably optically coupled gate drive signal, input circuitry, two power switching ports coupled to the VCGTO device output terminals, and an output circuit coupled across the device output terminals. The input circuitry includes an interface circuit and a drive circuit for driving the VCGTO device in response to the gate drive signal, while the output circuit includes a clamping mechanism and regulated clamp voltage circuit that maintains a safe, regulated maximum differential potential across the VCGTO device. The regulated clamp voltage circuit derives its operating potential from the high voltage switched by the associated GTO device, and provides therefrom a regulated low voltage potential that operates the associated input interface and gate drive circuitry. Because each module is identical, any non-simultaneous switching of the various devices in the series-coupled modules causes only a slight disparity in the amount of energy absorbed by each regulated clamp voltage circuit. Further, each module sees substantially the same differential potential between the module output ports, and operates independently regardless of where in the series-coupled chain the module is located. Dynamic voltage sharing among the various modules is assured, and the valve may be operated at a relatively rapid switching frequency, as no snubber is required.

Proceedings ArticleDOI
20 Jan 1993
TL;DR: In this paper, the speed and number of logic transitions of several different parallel multipliers are compared for arithmetic circuits with two-to-four-input AND and OR gates, and extensive simulation is used to evaluate their switching characteristics.
Abstract: For arithmetic circuits, it is important to maximize the speed and to minimize the power consumption, which may be accomplished by minimizing the product of the delay and the power consumption. The authors discuss the speed and the number of logic transitions (a measure of power dissipation for static CMOS circuits) of several different parallel multipliers. The circuits are constructed with inverters and two- to four-input AND and OR gates. Extensive simulation is used to evaluate their switching characteristics, and the results of the simulations are used to rank the multipliers on speed, size, and the number of logic transitions. >

Patent
David A. Harrison1, Abdul Malik1
04 May 1993
TL;DR: In this article, a programmable logic device (PLD) is used to carry out a specified logic function, where the PLD contains three levels of logic implemented as a plurality of functional blocks with AND and OR planes.
Abstract: A process of programming a programmable logic device (PLD) to carry out a specified logic function The PLD contains three levels of logic implemented as a plurality of functional blocks, each with AND and OR planes, and a programmable interconnect matrix or logic expander carrying out AND logic After providing such a PLD with specified size constraints and after specifying a logic function, the function is split or factored into subfunctions or factors A Boolean factorization procedure chooses factors by replacing pairs of product terms in the first factor with their supercube and minimizing the number input terms and product terms required Subfunctions or factors which are too large can be simplified by combining pairs of inputs in the interconnect matrix The product terms of a subfunction or factor can be ordered according to the number of input terms they have and assigned to the functional blocks one at a time Functional blocks which use many inputs or product terms per output can have some of their assigned subfunctions split so as to pack the PLD more densely Split subfunctions or factors are recombined in the interconnect matrix After assigning terms to functional blocks and the matrix, they are loaded into the PLD using a device programmer to configure the logic arrays in the PLD

Book ChapterDOI
01 Jan 1993
TL;DR: In this article the fundamentals of spectral design methods are reviewed and some new techniques that make application of such techniques to practical problems feasible are presented.
Abstract: Spectral methods have been used for logic design for many years. However, their use was limited to the synthesis and optimization of small digital circuits, due to the enormous complexity in computing the spectra of large logic functions. Recent developments in design automation and logic synthesis have prompted a new look at these methods, with emphasis on developing efficient computational procedures so that these powerful but complex methods can be used for the synthesis and optimization of larger logic networks. In this article we review the fundamentals of spectral design methods and present some new techniques that make application of such techniques to practical problems feasible.

Journal ArticleDOI
TL;DR: A comparison study was carried out between feedforward neural networks composed of binary linear threshold units and digital circuits and those generated by the regular partitioning algorithm and a modified Quine-McCluskey algorithm.

Book ChapterDOI
12 Oct 1993
TL;DR: The decomposition method has been implemented as a set of tools including reduction of attributes as well as functional decomposition and the experimental results show that the method is very efficient.
Abstract: In this paper we consider the problem of decomposition of information and logic systems and its implementation using decision and truth tables, respectively. The main reason behind using the described method is its economic representation of knowledge in information systems, knowledge base, data base and in all the other applications of information storing systems. Another potentially very promising area of application of decomposition is logic systems designing. This is because the novel hardware building blocks impose limitations on the size of circuits that can be implemented with them. The decomposition method has been implemented as a set of tools including reduction of attributes as well as functional decomposition. The experimental results show that the method is very efficient.

Patent
28 May 1993
TL;DR: A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs as discussed by the authors, and each output is generated by a pair of NMOS transistors.
Abstract: A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.

Journal ArticleDOI
TL;DR: In this paper, a wavelength selective optical logic (WSOL) element that uses monolithically integrated wavelength-selective optical input and output elements is described, where input optical signals are detected by photothyristors situated in an optical cavity which provides a highly selective response of a wavelength determined by the fabrication process.
Abstract: A wavelength selective optical logic (WSOL) element that uses monolithically integrated wavelength selective optical input and output elements is described. Input optical signals are detected by photothyristors situated in an optical cavity which provides a highly selective response of a wavelength determined by the fabrication process. Output signals are generated by vertical cavity surface emitting lasers, whose lasing wavelengths can also be specified during the fabrication process. A vertical integration of these input and output elements that is suitable for wavelength selective optical logic and wavelength selective optical interconnect applications is proposed. The proposed circuitry is easily cascadable so that arbitrarily complex optical logic functions can be performed by WSOL devices in series. Several of the possible logic functions are described, including OR and AND gates, an adder, and a flip-flop. >

Proceedings ArticleDOI
09 May 1993
TL;DR: In this paper, a post-placement netlist modifier which improves the performance of a placed netlist is presented, which is reached through three operations: buffer tree resynthesis, gate drive resizing and gate reconnection.
Abstract: A postplacement netlist modifier which improves the performance of a placed netlist is presented. Iterative technology remapping operations customize the most critical path timing for physical wire capacitances that are unique to a standard-cell placement. The improvement is reached through three operations: buffer tree resynthesis, gate drive resizing, and gate reconnection. Results show up to a 13% reduction in circuit timing for MCNC benchmarks that have already been optimized at the logic level for timing.

Journal ArticleDOI
TL;DR: In this paper, the SiNx is deposited at low temperature (50°C) by plasmaenhanced chemical vapor deposition in order to avoid distortion of the resist, and exhibits conformal coverage over the initial resist openings.
Abstract: 0.1 μm Y‐shape metal contacts for use as gates on GaAs metal–semiconductor field effect transistors (MESFETs) are produced using a novel SiNx deposition over features 1–2 μm wide, with subsequent etchback and gate metal deposition. Excellent across‐wafer uniformity (≤10%) on 3 in. φ substrates is achieved, yielding a simple technique for extending the resolution of conventional optical lithography tools. One of the key features in this method is the need to have an initial negative resist profile. The SiNx is deposited at low temperature (50 °C) by plasma‐enhanced chemical vapor deposition in order to avoid distortion of the resist, and exhibits conformal coverage over the initial resist openings. Submicron gate GaAs MESFETs fabricated by this technique have extrinsic transconductance, gm, value of ∼225 mS mm−1 at −0.5 V gate bias, and have comparable performance to devices fabricated using electron‐beam lithography to produce a more conventional T‐shape gate.

Patent
09 Dec 1993
TL;DR: In this paper, a liquid crystal display which can decrease parasitic capacitance developing at the crossing points of gate bus lines and data bus lines is proposed, which can improve step coverage of a data bus line.
Abstract: A liquid crystal display which can decrease parasitic capacitance developing at the crossing points of gate bus lines and data bus lines and can improve step coverage of a data bus line at the crossing point, comprising an insulating transparent substrate, a plurality of islandic conductive layers formed at the crossing points of the gate; lines and data lines on the insulating transparent substrate, a plurality of the gate lines formed on the substrate connecting opposing edges in one direction of each conductive layer, and a plurality of the data lines crossing above the conductive layers perpendicular to each gate line, isolated from conduction materials and gate lines.

Proceedings ArticleDOI
01 Jan 1993
TL;DR: Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented, and a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown.
Abstract: Several basic arithmetic and logic modules based on MVL (multiple-valued logic), including a multiplier and a pattern-matching accelerator, are presented. A micrograph of a 32-b*32-b SD (signed-digit) multiplier using multiple-valued bidirectional current-mode circuits is shown. Carry propagation during addition and subtraction is limited to one position to the left, providing totally parallel operation. Linear summation is simply by wiring. A mod-7 three-operand multiplier-adder based on residue arithmetic is also shown. Each residue digit is represented by a multiple-valued coding suitable for highly parallel computation, making it possible to achieve high-speed arithmetic operations. A quaternary nMOS logic-array chip for high-speed parallel pattern matching in a knowledge-information processing system is also shown. In addition, as an example of multiple-valued VLSI processors, a parallel-structure-based multiple-valued VLSI processor for high-performance digital control is shown. >

Patent
02 Jul 1993
TL;DR: In this paper, the threshold voltage of a MOS transistor to a desired one by applying voltage applied to the buried gate electrodes is controlled independently for each transistor or for each group of transistors irrespective of substrate impurity concentration, gate material, and gate insulating film thickness.
Abstract: PURPOSE:To set and control threshold voltage of a MOS transistor to a desired one by voltages applied to buried gate electrodes by constructing the buried gate electrode through a buried insulating film on the lower part of a single crystal ultra-thin film semiconductor layer completely insulated from a support substrate. CONSTITUTION:A title device is constructed that buried gates 61, 62 are buried at the bottom of a single crystal semiconductor layer through a buried gate insulating film 51. Hereby, threshold voltages of the transistors 1 and 2 are set mutually independently by setting voltages applied to the buried gate electrodes 61 and 62 to arbitrary values. More specifically such threshold voltages for SOI transistors are controlled independently for each transistor or for each group of transistors irrespective of the substrate impurity concentration, gate material, and gate insulating film thickness, and the like.

Patent
26 Aug 1993
TL;DR: In this paper, a flat panel display has an improved selection circuit for scanning row lines while data signals are applied to column lines for writing a selected image onto the pixel forming elements along the selected row line.
Abstract: A flat panel display has an improved selection circuit for scanning row lines while data signals are applied to column lines for writing a selected image onto the pixel forming elements along the selected row line. The number of row lines, N, is chosen to be the product of two numbers, P and Q and preferably N is a perfect square. A first timing circuit provides Q number of non-overlapping timing signals that each have P narrow clock pulses each of a width for writing data into one row the display; it also provides P number of non-overlapping timing signals that each have clock pulses with a width of Q write operations. For each row line of the display, the selection circuit has an AND logic circuit that responds to one wide pulse clock line and one narrow pulse clock line to connect the row line to a voltage to enable the pixel forming elements to turn on in a write operation. Another logic circuit for each row line selectively connects the line to a voltage to inhibit the turn on of the pixel forming elements. This circuit has a single gate that responds to the complement of the associated narrow pulse clock signal, and this gate closes to isolate a selected line from the inhibiting voltage. The gate is open for only a minimum time so that an unselected line with this gate open can not float electrically to a voltage that could allow its pixel elements to turn on.

Patent
Richard B. Huykman1
25 Aug 1993
TL;DR: In this paper, a PWM power supply combines the advantages of pulse width modulator circuitry with linear circuitry to provide power supply operation over an extended input range with no dropout of power supply output and no adverse effect on a load.
Abstract: A pulse width modulated (PWM) power supply combines the advantages of pulse width modulator circuitry with linear circuitry to provide power supply operation over an extended input range with no dropout of power supply output and no adverse effect on a load. The PWM circuitry includes input voltage scalers, control logic, mode detectors, an inductor, a diode switch and a capacitor and the linear circuitry includes a transistor, transistor voltage scaling and gate driver logic.

Patent
Nagatoshi Kadota1
27 Apr 1993
TL;DR: In this article, the output of an AND gate is kept at the "H" level for the turn-off time and is returned to the "L" level after the turnoff operation is completed.
Abstract: A driving signal is supplied to the gate of an IGBT through a first switching element. The gate of the IGBT is grounded via a resistor and a second switching element. An output (short circuit detection signal) of an AND gate, to which the driving signal and an output signal of the IGBT are supplied, is supplied to the first switching element via a first delay circuit and supplied to the second switching element via a second delay circuit. The second delay time is larger than the first delay time. In the normal operation, the driving signal is set to an "L" level to instantaneously turn off the IGBT. The output of the AND gate is kept at the "H" level for the turn-off time and is returned to the "L" level after the turn-off operation is completed. The first switching element is turned off when the first delay time has passed after the level of the driving signal is changed. At this time, the IGBT is already turned off. When the short circuit is detected, the output of the AND gate is not returned to the "L"level if it is once set to the "H" level so that the first switching element will be turned off to isolate the IGBT. Then, the second switching element is turned on when the second delay time has passed after the detection of the short circuit, permitting charges stored in the IGBT to be discharged to turn off the IGBT.