Showing papers on "AND gate published in 1994"

Semiconductor integrated circuit device and production method thereof

Abstract: The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal (22) is connected to a plurality of input terminals (19 to 21) through source-drain paths of active devices (M13 to M16) connected in the tree form, and gate electrodes of the active devices (M13 to M16) are connected to other input terminals (15 to 18). Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.

A Gate-Delay Model for High-Speed CMOS Circuits

Abstract: As signal speeds increase and gate delays decrease for high-performance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gate-output impedances make it more difficult to empirically characterize gate-delay models. Moreover, the single-input-switching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today.s high-speed logic paths. In this paper a new empirical gate delay model is proposed. Instead of building the empirical equations in terms of capacitance loading and input-signal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived k-factor models and switch-resistor models to efficiently: 1) handle capacitance shielding due to metal interconnect resistance, 2) model the RC interconnect delay, and 3)provide tighter bounds for simultaneous switching.

Logic block with look-up table for configuration and memory

Abstract: A logic block for a field programmable logic device which is of the type using memory bits in a look-up table to provide any function of several inputs, and which uses additional memory bits to control aspects of the configuration, achieves a smaller size by replacing memory bits which control some configuration choices of the logic block with multiplexers which alternately select a default configuration or allow the look-up table memory bits to control the configuration. Thus the memory bits perform an alternate function of serving as a look-up table to generate a function, and controlling gates such as multiplexers, XOR gates or AND gates to generate a function.

Programmable logic array and data processing unit using the same

Abstract: A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.

Layout Driven Logic Synthesis for FPGAs

Abstract: In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Logic synthesis for field-programmable gate arrays

Abstract: In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices. >

Ferroelectric non-volatile memory unit

Abstract: An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant ef and the gate insulator has a dielectric constant eg. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf<5×Cg, Af≦2Ag, b≧2a, and eg≧ef/8.

Timing analysis for logic optimization using target library delay values

Abstract: A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.

EEPROM and logic LSI chip including such EEPROM

Abstract: Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivity type and a gate electrode, a well of a second conductivity type provided in the substrate, a plate electrode formed on the well with an insulating layer interposed therebetween, and at least one region of the first conductivity type formed in the well adjacent to the plate electrode. The gate electrode and the plate electrode are connected in common and act as a floating gate, and the well acts as a control gate.

Circuit for fast carry and logic

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide an IC incorporating a voltage comparator circuit which is operated at a low voltage, has a small pattern area and improved detecting precision. SOLUTION: This semiconductor integrated circuit incorporates a voltage comparator circuit 10 which is provided with a PMOS transistor P1 whose source is connected to a VDD1 node, and whose drain and gate are interconnected, an NMOS transistor N1 whose drain is connected to the drain of the PMOS transistor, and whose source is connected to a GND node, and whose gate is applied with bias potential, a PMOS transistor P2 whose source is connected to a VDD2 node, and an NMOS transistor N2 whose drain is connected to the drain of the PMOS transistor, and whose source is connected to the GND node, and whose gate is applied with the same bias potential as that of the NMOS transistor N1. Then, signals in different logical levels are outputted from the drain of the PMOSFET according toe the compared result of the scales of the VDD1 and VDD2.

Method to ensure isolation between source-drain and gate electrode using self aligned silicidation

Abstract: A method for fabricating MOSFET devices with shallow source and drain diffusions, and high yielding self aligned refractory metal silicides was accomplished. This method involves forming a source and drain polysilicon diffusion layer, opening an hole in the polysilicon for the gate region, and fabricating oxide sidewalls in the hole to isolate the source and drain from a polysilicon gate. A polysilicon gate is than formed with a shape that will not allow the sides of this gate to experience subsequent metal deposition. A low temperature silicidation process than results in an absence of source and drain to gate polysilicon shorting or bridging, due to this unique gate polysilicon shape.

Method of producing stepped wall interconnects and gates

Abstract: A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer is formed over the conductive layer, patterned and developed. The conductive layer is etched after which the first photoresist layer is removed. A second photoresist layer is formed over the integrated circuit, patterned and developed. The remaining regions of the conductive layer forming an interconnect or a gate are partially etched to form two-tiered stepped sidewalls.

Apparatus for data communication switching

Abstract: A serial communication apparatus for directing data from a plurality of data input devices to a single data output device comprising a plurality of serial input connectors, a serial output connector, and logic and driver circuitry. The logic and driver circuitry automatically regulate the conditions under which a data input device transmits data to the data output device. In the illustrated embodiment of four data input devices, when all are idle, any of them may transmit data to the output device. If one data input device attempts to transmit data while the another data input device is transmitting data, then the logic and driver circuitry causes the second input device to pause until the first input device data transmission is complete. If both input devices attempt simultaneous data transmission, the logic and driver circuitry resolves the contest and allows only one data input device to transmit to the output device at a time.

Method and apparatus for floating point to fixed point conversion with compensation for lost precision

Abstract: A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit. A mask is generated by a lookup table according to the number of bits to be truncated. The mask supplies a logic 1 to one input of each such corresponding gate; the other input of each gate is driven by the bit to be truncated. If any such bit to be truncated is a one, then the output of the corresponding gate will be true. The outputs of all these AND gates or OR'ed together and the result stored in a latch; a SET latch then indicates the impending truncation of at least one 1. After the conversion the fractional portion of the destination register is checked to see if it is all zeros. If it is, and if the latch is also SET, then the least significant bit of the fractional portion of the destination register is forced to be understood as a 1 when the register is read.

Floating gate memory device having discontinuous gate oxide thickness over the channel region

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide. The cell resulting from the process has increased coupling coefficient, easier programmability, and better storage of the charge on the floating gate than a conventional cell.

Degenerate wavelength operation of an ultrafast all-optical AND gate using four wave mixing in a semiconductor laser amplifier

Abstract: A new, ultrafast, all-optical AND gate that operates on input signals at the same wavelength using four-wave mixing in a semiconductor laser amplifier is presented. Successful operation of the gate on 20 ps pulses modulated at 3 Gbit/s is descrihed. The device has applications in photonic networks operating at > 100 Gbit/s.

Sagnac fiber logic gates and their possible applications: a system perspective

Abstract: The Sagnac all-optical fiber logic gate functions as a two-input and gate, a two-input and gate with one inverting input, or both. The fiber logic gate is pipelined and has a fixed latency. This latency has no effect on feed-forward combinatoric circuits. The latency can be used to time multiplex circuits or to time multiplex gates to emulate a circuit. Possible applications such as a bit-jitter-tolerant communications system, an asynchronous communications system, a bit-interleaved self-routing switching system, an exchange/bypass permutation unit, and a folded universal state machine are discussed.

Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits

Abstract: A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.

Scan flip-flop with power saving feature

Abstract: A flip-flop has both a system output and a scan output. A system output signal for the flip-flop is placed on the system output. When the flip-flop is in a normal operating mode, a scan output signal on the scan output is held at a static logic level. When the flip-flop is in a scan mode, the scan output signal on the scan output transitions between logic 1 and logic 0 synchronous with transitions of the system output signal on the system output.

Method of making an electrically erasable programmable memory device with improved erase and write operation

Abstract: An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrically erasable programmable read only memory device.

Verification of asynchronous interface circuits with bounded wire delays

Abstract: We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence under various modes of operation.

Method and apparatus for timing acquisition of partial response class IV signaling

Abstract: A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X n and X n-1 . The logic uses these values to determine the next value X n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.

Field programmable gate array providing contention free configuration and reconfiguration

Abstract: A circuit and method in a field programmable gate array (FPGA) for eliminating programming contentions which occur during array configuration comprises a switching matrix of crossing lines, in which cross points, called programmable interconnection points (PIPs), are connected by configuration transistors. The configuration transistors can be programmed to connect the lines at the PIPs or to leave the lines unconnected. Output drivers are selectively connected by the PIPs to the signal lines. Prior to the configuration and reconfiguration of the FPGA, drivers to the gate array are disabled to prevent potentially catastrophic driver contention. The contention eliminating circuit of the present invention holds the logical values of the output buffers to a single logic level until programming has been completed. The circuit of the preferred embodiment comprises a two input AND gate which combines the incoming data signals with a gating signal. The first set of AND gate inputs receives and transmits the incoming data used for driving the input buffers. The second set of inputs to the AND gates receives enable signals which control the propagation of the input data to the PIP array until programming of the PIPs is completed.

Row driving circuit for memory devices

Abstract: A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14. S13 and S14 provide a negative erase voltage to both the gate and drain of P4. In addition, S13 and S 14 can bias P4 into linear mode, allowing P4 to operate a leaker transistor, pulling the row down to a deselect voltage.

Active matrix circuit

Abstract: PURPOSE:To optimize a circuit by doping substantially any one of N or P type impurities and doping both N and P type impurities into the source-drain of a TFT in the peripheral circuit having same conductivity type as that of the TFT in an active matrix circuit. CONSTITUTION:An insular crystalline semiconductor region 103 is formed, at first, on a substrate 101 and a gate insulating film 104 is deposited thereon followed by formation of a gate electrode 105 and a gate wiring 106 using an appropriate material. Subsequently, doping impurity ions are accelerated and projected to form an impurity region 109 in the semiconductor region using the gate electrode 105 as a mask. Thereafter, an insulator coating 110 is formed while covering the gate electrode and gate wiring. The insulator is etched preferentially in the direction substantially perpendicular to the substrate by anisotropic etching. Consequently, substantially triangular side walls 111, 112 are left and impurity doping is performed using the side walls as a mask.

Fast static cascode logic gate

Abstract: A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state. In this way, the driver circuit receives a full source voltage representing the first state.

Device and method for binary-multilevel operation

Abstract: To provide a binary-multilevel OR gate, a binary-multilevel AND gate, a binary-multilevel EXCLUSIVE OR gate and their operational methods, which enable direct logic operations between multilevel logic values and binary logic values, including logic operations between binary numbers, the present invention comprises a switch for performing binary-multilevel OR gate operations, which select and output according to binary logic signal values only an input out of its both inputs of a multilevel logic signal and a maximum value of the multilevel logic signal; a switch for performing binary-multilevel AND gate operations, which select and output according to binary logic signals only an input out of its both inputs of multilevel logic signals and a minimum value of the multilevel logic signal; and a switch for performing binary-multilevel EXCLUSIVE OR gate operations, which select and output according to binary logic signals only an input out of its both inputs of a multilevel logic signal and the complementary value of the multilevel logic signal. Accordingly, the present invention has an advantage of enabling the construction of economical and simple circuits.