Showing papers on "AND gate published in 1996"

Gate oxide scaling limits and projection

Abstract: MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient for MOSFET scaling to 0.05 /spl mu/m.

Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs

Abstract: Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.

A capacitive threshold-logic gate

Abstract: A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

Low temperature method of forming gate electrode and gate dielectric

Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.

Method for fabricating metal oxide field effect transistors

Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET. The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask. Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode.

Gate array having highly flexible interconnection structure

Abstract: A basic cell structure of a gate array that allows wiring in a macro cell is implemented solely by using first layer metallic wires and entails neither performance deterioration nor an increase in sell size. The basic cell of the gate array comprises a pMOS transistor having two FETs connected in series to each other and an nMOS transistor also having two FETs also connected in series to each other. The pMOS transistor and the nMOS transistor are formed on a substrate and arranged in parallel to each other, and gate electrodes corresponding to the FETs are commonly provided for the pMOS transistor and the nMOS transistor. In this structure, a first auxiliary wire is provided between the gate electrodes on the same layer as the gate electrodes. A second auxiliary wire is provided between adjacent basic cells also on the same layer as the gate electrodes. Wiring in a macro cell can be completed by using the first and second auxiliary wires of different types to form a two-dimensional structure. That is, wiring can be completed solely by using the first layer metallic wires.

Useful-skew clock routing with gate sizing for low power design

Abstract: Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skew may allow a larger timing budget for gate sizing. We construct a useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree configurations. This is complemented by a bi-partitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11% to 22% total power reduction over previous methods of clock routing with zero-skew or single fixed skew bound and separately sizing logic gates.

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Abstract: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginning to be addressed in the literature. The effect of proximity of input transitions can be significant on the delay and output transition time. The few attempts that have addressed this issue are based on a series-parallel transistor collapsing method that reduces the multi-input gate to an inverter. This limits the technique to CMOS technology. Moreover, none of them discuss the appropriate choice of voltage thresholds to measure delay for a multi-input gate. In this paper, we first present a method for the choice of voltage thresholds for a multi-input gate that ensures a positive value of delay under all input conditions. We next introduce a dual-input proximity model for the case when only two inputs of the gate are switching. We then propose a simple approximate algorithm for calculating the delay and output transition time that makes repeated use of the dual-input proximity model without collapsing the gate into an equivalent inverter. Comparison with simulation results shows that our method performs quite well in practice.

System integration of DRAM macros and logic cores in a single chip architecture

Abstract: A chip architecture standard merges dynamic random access memory (DRAM) macros and logic cores. The standard from merged DRAM and logic design provides the advantages of simplicity, high read and write access rates, lower power dissipation and noise suppression in system-on-chip designs. The architecture depends upon balanced clock distribution for its high performance and low clock skew to the DRAM macros and logic cores. Balanced wirings from output drivers of the control logic to corresponding inputs of the different DRAM macros minimize differences in address and control signal delays. Separated Vdd and Gnd power grids distribute power to the DRAM macros and the logic cores and incorporate decoupling capacitor arrays to provide noise suppression between the DRAM macros and logic and to minimize di/dt power supply fluctuations on chip performance.

Programmable modulo-K counters

Abstract: A modulo-k counter or frequency divider is a binary counter that provides an output pulse for every k clock pulses. We describe a modulo-k counter that is programmable and synchronous, with an implementation that is regular and well suited for VLSI. The period of the counter is equal to the delay of a half-adder, a 3-input AND gate, and a latch, independent of the size of the counter. This is just as fast as one proposed by Ercegovac and Lang (1989), but it has a simpler design, uses less area, and is more flexible in that it is easier to change the modulus.

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

Abstract: The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.

Null convention threshold gate

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL.

Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells

Abstract: An integrated process for forming a 4T SRAM and a floating gate memory, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a floating gate over a field oxide region in a second memory region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates, except over the floating gate in the second memory region, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a control gate over the floating gate, and to form a load resistor for the SRAM.

Semiconductor device and display driving device using the same

Abstract: PROBLEM TO BE SOLVED: To make a leakage current small, to perform high integration, to perform formation with less processes and to make an output level be appropriate by performing constitution by the transistors of the same conductive type. SOLUTION: The respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input (IN) is inverted is impressed from an inverted input (IN with upper bar) side to the gate of the P type transistor 14. Then, the source and drain of the P type transistor 12 are interposed between the inverted input (IN with upper bar) to the gate of the P type transistor 14 and a capacitor 15 whose one end is connected between the P type transistor 12 and the gate of the P type transistor 14 and other end is connected between the P type transistor 13 and connection point of the P type transistor 14 is interposed. Thus, a Low level outputted from an output terminal (OUT) is corrected so as to be a potential equivalent to a ground level.

Flexible circuitry and method for detecting signal patterns on a bus

Abstract: Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output. One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden. The first and second comparison outputs may be generated by bit-wise comparing first and second portions of the bus with first and second expected signal patterns. The logical AND of the respective comparison results may be treated as the first and second comparison outputs, or they may be treated as first and second intermediate bits. These first and second intermediate bits may be ORed with first and second mask bits, and the results may be treated as the first and second comparison outputs. The outputs of the two OR operations may also be EXCLUSIVE ORed with first and second negate bits, respectively.

Method for manufacturing semiconductor device incorporating DRAM section and logic circuit section

Abstract: In a method for manufacturing a semiconductor device incorporating a DRAM section and a logic circuit section, a refractory metal layer is formed to cover a bit line of the DRAM section, and a gate electrode and impurity diffusion regions of the logic circuit section. Then, a heating operation is performed upon sadi refractory metal layer, so that metal silicide layers are formed in the bit line of the DRAM section, and the gate electrode and the impurity diffusion regions of the logic circuit section.

Low-power design technique for ASICs by partially reducing supply voltage

Abstract: In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing one to reduce power without performance degradation. As a result of application to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing became less effective. The CVS is considered to be a key technique toward the deep sub-micron age, in which the wire capacitance will be further dominant.

A parallel processing chip with embedded DRAM macros

Abstract: A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PE's are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.

Method for designing a semiconductor integrated circuit

Abstract: A semiconductor integrated circuit capabling of reducing a chip area by facilitating optimization of a chip layout and a method for designing the same has been provided. For given gate level connection description, use cell information designating gates which should be designed by employing the cell patterns prepared in advance is generated. When the gate level connection description is developed into the transistor level, hybrid connection description including mixedly transistor level and gate level is then generated by employing the cell patterns relative to the gates which being designated by the use cell information and by developing gates which being not designated by the use cell information into transistor level. A layout is then designed based on the hybrid connection description including mixedly the transistor level and the gate level.

Current mode null convention threshold gate

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Flat display data driving device using latch type transmitter

Abstract: A flat display driving device includes a gate driving circuit for sequentially and selectively applying a high voltage to a plurality of gate lines to drive them; a data driving circuit which includes a shift register for sequentially inputting one line of pixel data, a current source array which inputs one line of pixel data from the shift register, generates one line of current signals corresponding to each logic value of the pixel data and applies one line of current signals to the data lines and a latch type transmission array connected between the shift register and the current source array, for adjusting the supply time of one line of pixel data to be applied to the current source array, thereby driving the pixels on one horizontal line of the field emission display by the current signals for a predetermined time period; and a control circuit which processes a video signal into a series type of pixel data, supplies it to the data driving circuit and generates control signals required for the data driving circuit and gate driving circuit.

Semiconductor device with gate insulator film

Abstract: A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p- impurity region and p+ impurity regions. The p- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

Reliability of gate oxide grown on nitrogen‐implanted Si substrates

Abstract: Direct nitrogen implant into Si substrate prior to gate oxidation has been proposed to grow multiple gate oxide thicknesses on a single wafer. In this letter, we have studied the reliability of gate oxide grown on nitrogen‐implanted Si substrate. The effects of implant doses, sacrificial oxide thicknesses, and gate oxide thicknesses on gate oxide reliability have been investigated. It was found that there is a tradeoff between oxide thickness control and gate oxide reliability.

Liquid crystal display device and its fault correction method

Abstract: PROBLEM TO BE SOLVED: To make possible respectively correcting plural pixel faults on signal wiring by forming auxiliary capacity lines to a grid shape intersecting in respective pixels. SOLUTION: The auxiliary capacity lines 2 are formed on a glass substrate 1 in the grid shape, and a first insulation film layer 3 is formed on them so as to cover the whole glass substrate 1 surface, and further, gate signal wiring 4 and gate electrodes 4a in the shape branching from the gate signal wiring 4 in a branch shape are provided. A second insulation film layer 5 is provided on the gate signal wiring 4, and source signal wiring 6 are arranged in the shape orthogonally intersecting with the gate signal wiring 4 through the insulation film layer 5, and source electrodes 6a are branched from the source signal wiring 6 in the branch shape, and TFTs 9 are provided in the vicinity of crossing parts between the gate signal wiring 4 and the source signal wiring 6. COPYRIGHT: (C)1998,JPO

Liquid crystal display devices having redundant gate line driver circuits therein which can be selectively disabled

Abstract: A liquid crystal display including a driving circuit is provided. The LCD in which one gate line is driven by both left and right gate drivers includes a couple of switching means which are placed between the gate driver and gate line, the couple of switching means being activated and deactivated by switching control signals to switch the output of the gate driver. When one of the gate drivers does not operate, the output of the gate driver having the operational problem is prevented from being applied to the gate lines, by a switching operation. Therefore, even when only one of gate drivers operates, the display panel can function properly, thereby preventing the lowering of picture quality and improving product yield.

Phase locked loop circuit

Abstract: PURPOSE: To allow a voltage controlled oscillator to output a more clean frequency signal by reducing spurious radiation at both sides. CONSTITUTION: First and second AND gate elements 20a, 20b are provided after 1st and 2nd D flip-flop circuits 10a, 10b and a NAND gate element 11 of a phase discriminator 2 of the phase locked loop circuit. The 1st AND gate element 20a receives a 1st phase signal QV from the 1st D flip-flop 10a and a reset signal R from the NAND gate element 11 to provide an output of a 1st phase signal QV' to a main loop amplifier 4. The 2nd AND gate element 20b receives a 2nd phase signal QR from the 2nd D flip-flop 10b and the reset signal R from the NAND gate element 11 to provide an output of a 2nd phase signal QR' to the main loop amplifier 4.

Method of reducing overlap between gate electrode and LDD region

Abstract: A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the LDD region is substantially aligned with a lateral edge of the gate electrode. Preferably, the lateral portion of the gate electrode is removed using an isotropic etch. The method further includes forming a spacer adjacent to an edge of the gate electrode after removing the lateral portion, and then implanting a heavily-doped region using the spacer and gate electrode as an implant mask.

Open drain output driver having digital slew rate control

Abstract: An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

Integrated circuit memory devices with latch-free page buffers therein for preventing read failures

Abstract: Integrated circuit memory devices with latch-free page buffers therein include a page buffer for electrically coupling a bit line from an array of memory cells to a buffer output. The page buffers generate a first logic state at an output thereof when the bit line is at a first logic potential and a high-impedance logic state when the bit line is at a second logic potential, during a memory read operation. An output buffer is also provided for converting the high-impedance state and the first logic state generated by the page buffer to respective opposite logic states (e.g, logic 1 and logic 0). The bit line data is used to directly trigger the appropriate state of the page buffer output by coupling a gate of an insulated-gate isolation transistor to the bit line data and then reading the source of the isolation transistor as the page buffer output.

Master-slave bistable latch with clock input control

Abstract: It is an object to obtain a semiconductor integrated circuit with reduced power consumption without reducing operation speed. In clock input control means (27), an exclusive OR gate (26a) receives comparison data (S1 and S2) and an NAND gate (27a) receives output of the exclusive OR gate (26a) and a reference clock (T) and outputs its output, a control signal (SC1) to an AND gate (G1) and an AND gate (G2) in a data holding portion (31a). An exclusive OR gate (26b) receives comparison data (S3 and S4) and an NAND gate (27b) receives the output of the exclusive OR gate (26b) and the reference clock (T), and outputs its output, a control signal (SC2) to an OR gate (G5) and an OR gate (G6) in a data holding portion (31b). Appropriately selecting the comparison data (S1-S4) allows data transfer at high speed of input data (D), output data (Q), inverted output data (QC), and so forth.