Showing papers on "AND gate published in 1997"

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Adjustable output driver circuit

Abstract: An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.

Adjustable output driver circuit having parallel pull-up and pull-down elements

Abstract: An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.

Short channel self-aligned VMOS field effect transistor

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Data security system and method

Abstract: A data security system and method for providing a cryptographic process such as the Data Encryption Standard comprises a microprocessor having a programmable hardware element such as a field programmable gate array interfaced to the processor bus. The predetermined ordered sequence of operations which form the cryptographic process are parsed into hardware-centric operations such as bit manipulations, table look-ups and logic operations which are efficiently performed in hardware, and into software-centric operations such as data processing and state machine control. Hardware-centric operations are performed in the programmable hardware device, and overall control of the system is performed under microprocessor control.

Si/SiGe vertical junction field effect transistor

Abstract: A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

Dynamic internal testing of CMOS circuits using hot luminescence

Abstract: Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the dynamics of all the gates of the circuit are simultaneously measured. This noninvasive technique can be extended to smaller device size, as well as probing from the backside of the wafer. The optical emission may provide an alternative to electron beam testing for measuring the dynamics of high-speed CMOS circuits.

Reduced area gate array cell design based on shifted placement of alternate rows of cells

Abstract: A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.

Thin film transistor matrix device

Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.

Configurable logic block with AND gate for efficient multiplication in FPGAS

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Postlayout logic restructuring using alternative wires

Abstract: In this paper, we propose a layout-driven synthesis approach for field programmable gate arrays (FPGA's). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the chance of successful routing. A redundancy addition and removal technique is used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Liquid crystal display devices having improved screen clearing capability and methods of operating same

Abstract: Liquid crystal display devices include an array of liquid crystal display cells arranged as a plurality of columns of display cells electrically coupled to respective data lines and a plurality of rows of display cells electrically coupled to respective gate lines. A gate line on/off voltage generator and gate line driving circuit are provided to drive at least a first gate line with a turn-on voltage of first polarity (e.g., positive voltage) and simultaneously driving at least a second gate line with a turn-off voltage of second polarity (e.g., negative voltage). First and second screen clearing circuits are also provided to improve the screen clearing capability of the liquid crystal display device. The first screen clearing circuit can be electrically coupled to the first gate line to perform the function of driving the first gate line from the turn-on voltage (e.g., positive voltage) to a ground reference voltage upon termination of a power supply signal; and the second screen clearing circuit of different design can be electrically coupled to the second gate line to perform the function of driving the second gate line from the turn-off voltage (e.g., negative voltage) to the ground reference voltage upon termination of the power supply signal. These driving functions may act to increase the conductivity of the TFTs in the "off" display cells and thereby improve the rate of charge leakage from the storage capacitors and the liquid crystal capacitors therein.

Output buffer circuit

Abstract: In order to prevent a through current from flowing to a set of MOS transistors in the final stage constituting a push-pull buffer circuit, a reset circuit which performs delaying operation and logic decision by separately receiving signals from two inverter gate groups of a control system and output system arranged in the preceding stage of the transistors is provided. Therefore, the flowing of the through current to the transistors can be prevented even when an input-output circuit consistinng of two power source systems becomes unstable when the power sources are turned on or off and such logic on which a through current flows to the final stage due to a signal output of a signal level converting circuit is generated because the rest circuit forcibly cancels the logic by applying feedback.

Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation

Abstract: In a logic integrated DRAM LSI with SIMD architecture, a intentional clock skew is introduced for both between DRAM blocks and between logic blocks due to reduce the magnitude of peak current, operation frequency and number of I/O are defined for both DRAM blocks (frequency f M , I/O number m) and logic blocks (frequency f N , I/O number n) to keep the relation of f.sub.M ×m=f.sub.N ×n, address out of order scheme is introduced to achieve a high-speed and low-power DRAM access.

Method of forming a MOSFET using a disposable gate and raised source and drain

Abstract: A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Abstract: This paper presents a new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is useful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes together form the feasible solution space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explore various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible configurations, we adopt a simulated annealing approach to avoid being trapped in a local optimal configuration. This is complemented by a bi-partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of clock routing with zero-skew or a single fixed skew bound and separately sizing logic gates. This is achieved at no sacrifice of clock frequency.

Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory

Abstract: A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

Thermionic emission model of electron gate current in submicron NMOSFETs

Abstract: A thermionic emission model based on a non-Maxwellian electron energy distribution function for the electron gate current in NMOSFET's is described. The model uses hydrodynamic equations to describe more correctly the electron transport and gate injection phenomena in submicron devices. A generalized analytical function is used to describe the high-energy tail of the electron energy distribution function. Coefficients of this generalized function are determined by comparing simulated gate currents with the experimental data. This model also includes the self-consistent calculation of the tunneling component of the gate current by using the WKB approximation, and by using a more accurate representation of the oxide barrier by including the image potential. Good agreement with gate currents over a wide range of bias conditions for three different technological sets of devices are demonstrated by using a single set of coefficients.

Method of forming a MOSFET using a disposable gate with a sidewall dielectric

Abstract: A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222,223, and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g., using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214). The disposable gate (220) is then removed and the gate dielectric (210) and gate electrode (212) are formed.

Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Distributed amplifier logic designs

Abstract: A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.

Non-volatile programmable CMOS logic cell and method of operating same

Abstract: A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The first transistor is coupled in series between a first voltage supply terminal and an output terminal, while the second transistor is coupled in series between a second voltage supply terminal and the output terminal. The first and second transistors share a common floating gate and a common control gate, which extends over the common floating gate. The floating gate has substantially the same layout as the control gate. When the floating gate is programmed to store charge of a first polarity, the programmable logic cell enters a non-volatile first state and provides an output signal having a first logic state. When the floating gate is programmed to store charge of a second polarity, the programmable logic cell enters a non-volatile second state and provides an output signal having a second logic state. When the floating gate is programmed to store a neutral charge, the programmable logic cell enters a third state in which the programmable logic cell provides an output signal representative of a predetermined logic function in response to one or more input signals. This logic function can be, for example, an inverter function, a logical NAND function, or a logical NOR function. The output terminal of the programmable logic cell can be coupled to a pass transistor of a programmable interconnect structure or to a configurable logic block of a field programmable gate array.

The dual-gate W-switched power MOSFET: a new concept for improving light load efficiency in DC/DC converters

Abstract: A merged dual-gate power MOSFET is described which greatly improves the light-load energy efficiency of high-speed (f>1 MHz) low-voltage DC/DC conversion by dynamically reducing input capacitance and gate drive losses during low-current load conditions. The W-switched MOSFET concept is experimentally verified using a TrenchFET employing a 30/spl times/ reduction in input capacitance during light load. Efficiency improvements better than 25% and a decade increase in useable load current were confirmed for a 1-cell Li ion to 5 V boost converter, without adversely affecting the converter's transient response. Various figure-of-merits for W-switched MOSFETs are also proposed to analyze the limits of W-switching.

A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime

Abstract: Hot-carrier degradation in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions such as stress bias, oxide thickness, gate length, and channel-type dependencies for the first time. It was confirmed that n-MOSFETs with thinner gate oxides have higher hot-carrier reliability in the direct-tunneling regime from 1.5 nm to 3.8 nm. For p-MOSFETs, little degradation was observed under all conditions of stress bias, oxide thickness, and gate length. These results indicate that ultra-thin gate oxides in the direct-tunneling regime have extremely high hot-carrier reliability.

Low noise, high current-drive MOSFET structure for uniform serpentine-shaped poly-gate turn-on during an ESD event

Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Programmable logic device placement method utilizing weighting function to facilitate pin locking

Abstract: A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformulation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

Abstract: CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3 nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline n/sup +/ poly gate. It is found that the PVD TiN has higher metal-to-SiO/sub 2/ barrier height (/spl sim/3.77 eV) than that of the CVD TiN (3.62 eV). The CVD W/PVD TiN gates without high temperature (>900 C) RTP anneal show good electrical characteristics on 3 nm gate oxide, and the CVD TiN is less favorable due to its high impurities. High temperature anneal cause fluorine in CVD W to diffuse and interact with the gate oxide which adversely affect the gate oxide integrity (GOI). The remote plasma nitrided gate oxide (RPNO) provides a barrier between the TiN and gate oxide, and thus prevents or reduces the F-SiO/sub 2/ interaction, resulting in metal gate GOI comparable to that of poly gate. The CVD metal gate is a good candidate for the non-conventional, high aspect ratio grooved gate structures due to its good conformality.

Field effect transistor having multiple gate electrodes surrounding the channel region

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

All-optical wavelength coded logic gates

Abstract: All-optical logic gates in which binary words are encoded using wavelength. A method and apparatus for processing information in this wavelength encoded format is provided. The processing may occur entirely in the optical domain. This approach is modular and enables construction of logic gates using custom wave guide chips that can be mass-produced in a manner similar to that of conventional electronic digital chips. Specific gates, such as AND, OR, EXOR, or NAND, may be "programmed" into a given chip during its fabrication to encode the desired truth table. The output states of the chip are determined by ultrafast mixing of binary encoded wavelengths in a semiconductor optical amplifier. The result is a new wavelength having a relationship to the input wavelengths determined entirely by the desired truth table. The possible clock-rates for these gates can be exceedingly high, such as several hundred Gigabits/second. The product of integer word length "N" and gate clock speed can exceed several Terabits/second and may be as high as the overall optical bandwidth of the system. Complicated multi-input functions may be constructed using this approach and dynamically programmable functions may be built in which either electrical or optical signals reconfigure a set of gates by reprogramming the inverter operations in the chips.