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Showing papers on "AND gate published in 1999"


Proceedings ArticleDOI
01 Jun 1999
TL;DR: This work proposes to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree and verified the effectiveness of this approach on an industry design.
Abstract: Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these methods use simplified interconnect and gate delay models. These models may lead to inferior solutions since the optimized objective is only an approximation for the actual delay. We propose to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree. We have verified the effectiveness of our approach on an industry design.

116 citations


Patent
Carlos Augusto1
26 Aug 1999
TL;DR: In this paper, the authors proposed a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order.
Abstract: The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order. The process flow of the present invention provides for the implantation and thermal processing of the wells and junctions prior to the growth of a channel or the deposition of the gate stack. By implanting and annealing the wells and junctions prior to the formation of the channel and gate, the present invention allows a greater variety of materials to be utilized as the channel and gate materials than are available under process flows currently known; undoped materials may be used to form the channel, metal oxides and similar materials with large dielectrics may be used to form a gate stack, and barrier metals and pure metals (copper, tungsten, etc.) may be used as gate electrodes. The present invention also provides for the selective epitaxial growth of a channel material elevated above the surface of a wafer containing a well and junctions. By providing an elevated channel, higher mobility may be achieved; thereby enabling a higher current flow at a lower voltage through a semiconductor device.

106 citations


Patent
03 Sep 1999
TL;DR: In this article, an envelope tracking and gate biasing circuit is used to adjust the gate bias inversely with the changes in the drain voltage, which increases the voltage conveyed to the power amplifiers.
Abstract: A radio frequency signal (FIG. 2, 205) is sampled and the sample is conveyed to a video detector (220). The detected envelope amplitude is sent to an envelope tracking circuit (280), a comparator (230), and an envelope tracking and gate biasing circuit (240). Based on the instantaneous value of the envelope amplitude, the comparator (230) selects one of the available supply voltages (340) via switch drivers (270). The selected one of the available supply voltages (340) is adjusted by the envelope tracking circuit (280) and the resulting voltage output (282) is supplied to the drains of the power amplifiers (390), thus enabling operation near saturation. As the instantaneous value of the envelope amplitude increases, the comparator (230) selects higher supply voltages (340) which increases the voltage conveyed to the power amplifiers (390), thereby increasing their power output. In order to maintain constant gain performance, the envelope tracking and gate biasing circuit (240) modifies the gate bias inversely with the changes the drain voltage.

104 citations


Patent
01 Jun 1999
TL;DR: In this article, a polysilicon layer is used to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask.
Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode

87 citations


Patent
10 Sep 1999
TL;DR: In this paper, the fabrication of a lateral RF MOS device with non-diffusion connection between source and substrate is described, and the top of each gate is silicided once the protective layer of silicon nitride is removed.
Abstract: Methods of fabrication of a lateral RF MOS device (10, Fig. 1) having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure (Fig. 18). In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure (Fig. 19). Both sides of each gate are oxidized thus preventing possible shorts between source and gate regions and between drain and gate regions. The top of each gate is silicided once the protective layer of silicon nitride is removed.

81 citations


Patent
09 Jul 1999
TL;DR: In this article, an oxidation barrier is formed on the sidewalls of a metal control gate to protect it from oxidation during the fabrication of a polysilicon floating gate, which is useful in reducing peeling, stress and related oxidation problems.
Abstract: Floating gate stacks having a metal control gate and a polysilicon floating gate and their methods of fabrication that are particularly useful for floating gate memory cells and apparatus produced therefrom. The metal control gate permits reduced gate resistance and gate height over polysilicon or silicide control gates. An oxidation barrier is formed on sidewalls of the metal control gate to protect it from oxidation during oxidation of sidewalls of the polysilicon floating gate. The oxidation barrier is useful in reducing peeling, stress and related oxidation problems when using metals such as tungsten in the metal control gate.

75 citations


Journal ArticleDOI
TL;DR: In this article, an exhaustive experimental study of the high-frequency noise properties of MOSFETs in silicon-on-insulator (SOI) technology is presented, where various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters.
Abstract: An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown.

73 citations


Patent
16 Apr 1999
TL;DR: In this article, the fabrication of a lateral RF MOS device with non-diffusion connection between source and substrate is described, and a quasi-mesh silicided gate structure is presented.
Abstract: Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure. Both sides of each gate are oxidized thus preventing possible shorts between source and gate regions and between drain and gate regions. The top of each gate is silicided once the protective layer of silicon nitride is removed.

72 citations


Journal ArticleDOI
Kunihiro Suzuki1
TL;DR: In this article, the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator was investigated and it was shown that the model commonly used for parasitic capacitation is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices.
Abstract: We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model.

65 citations


Patent
13 Sep 1999
TL;DR: In this paper, a body diffusion layer is formed between the gate layers, and afterwards, a source diffusion layer connected to a source electrode and an identical process is used to form a diffusion layer between the two diffusion layers.
Abstract: Plural grooves are formed in a main surface of semiconductor layers on semiconductor substrate, and gate layers connected to a gate electrode are formed in the plural grooves through a gate insulating film, and then a body diffusion layer is formed between the gate layers, and afterwards, a source diffusion layer connected to a source electrode and a source diffusion layer connected to a source electrode are formed in an identical process.

58 citations


Patent
16 Nov 1999
TL;DR: In this paper, a TFT of new structure in which the gate electrode overlaps with the LDD region is presented. But the gate electrodes do not overlap with the source-drain region.
Abstract: The present invention is directed to a TFT of new structure in which the gate electrode overlaps with the LDD region and a TFT of such structure in which the gate electrode does not overlap with the LDD region. The TFT is made from crystalline semiconductor film and is highly reliable. The TFT of crystalline semiconductor film has the gate electrode formed from a first gate electrode 113 and a second gate electrode in close contact with said first gate electrode and gate insulating film. The LDD is formed by ion doping using said first gate electrode as a mask, and the source-drain region is formed using said second gate electrode as a mask. After that the second gate electrode in the desired region is selectively removed. In this way it is possible to form LDD region which overlaps with the second gate electrode.

Journal ArticleDOI
TL;DR: Results of investigations are presented on the implementation of an enzyme/inhibitor logic gate operating under the rules of Boolean algebra, and its operation relies on the conclusions reached regarding the optimal mode for controlling the inhibitory activity of proflavine.
Abstract: Molecular-scale logic systems will allow for further miniaturization of information processing assemblies and contribute to a better understanding of brain function. Of much interest are the pertinent biological systems, some of the basic components of which are biomolecular switching elements and enzyme-based logic gates. In this series of accounts, results of investigations are presented on the implementation of an enzyme/inhibitor logic gate operating under the rules of Boolean algebra. In this report (part 1 of the series), consideration is given to the experimental conditions-particularly the irradiation mode-that affect the performance of proflavine as inhibitor of alpha-chymotrypsin. Also, assessments are made on the reversibility of the process involved and the long-term stability of the system. Moreover, using a theoretical conformational analysis of proflavine and its reduction products, detailed features were established regarding their three-dimensional structure, partial charge distribution, and hydrophobicity. Accordingly, an understanding was reached as to the factors affecting the interaction between these compounds and the enzyme. In part 2 of this series, the actual implementation of an AND logic gate will be presented. This gate involves proflavine and a chemically derivatized alpha-chymotrypsin, and its operation relies on the conclusions reached in this report regarding the optimal mode for controlling the inhibitory activity of proflavine.

Patent
08 Feb 1999
TL;DR: In this paper, a gate driving circuit for shortening a switching period without destroying a gate type semiconductor element is proposed. But the circuit requires the gate type SINR element to be installed in the circuit.
Abstract: PROBLEM TO BE SOLVED: To provide a gate driving circuit for shortening a switching period without destroying a gate type semiconductor element. SOLUTION: This gate circuit 1 is provided with the gate type semiconductor element 5, a first on gate circuit for supplying a first on-gate current to the gate type semiconductor element 5 and a second on-gate circuit for starting the supply of a second on-gate current to the gate type semiconductor element 5 after the lapse of prescribed time after starting the supply of the first on-gate current.

Patent
14 Dec 1999
Abstract: PROBLEM TO BE SOLVED: To provide a test circuit capable of arbitrarily changing the constitution, and high in recycling possibility. SOLUTION: A semiconductor integrated circuit device is provided with a plurality of registers REG1-REG8 which are successively connected to each other, a switching circuit 1 connected between stages of the registers, and a register length judging circuit to output the bit width setting signal, and each switching circuit 1 is provided with an AND gate G1 and an EXOR gate G. When the corresponding data in the parallel control data S11-S17 is [1], the register output of the final stage is outputted without any change, and the corresponding EXOR gate G2 outputs the output of the AND gate G1, the register output of the previous stage, and the exclusive logical sum. When the corresponding data in the parallel control data S11-S17 is [1], the EXOR gate G2 functions as a feedback point. The bit width of MFSR and the position of the feedback point can be arbitrarily set by the logic of the externally fed parallel control data S11-S19.

Patent
05 Nov 1999
TL;DR: In this paper, a T-gate and salicide process was proposed to allow narrow bottom gate widths below 0.25 μm and wide top gate width to allow silicide gate contacts on the top of the T gate.
Abstract: A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 μm and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.

Patent
Lee Jueng-Gil1
11 May 1999
TL;DR: In this article, the gate lines and gate electrodes are formed to comprise a plurality of layers including an aluminum or related alloy first layer, a tantalum or related Alloy second layer on the first layer and an anodic oxide containing tantalum (e.g., TaO5) top layer.
Abstract: Methods of forming liquid crystal display devices include the steps of forming a gate line and a gate electrode on a face of a transparent substrate and then forming an insulating layer (e.g., Si3N4) on the gate line and gate electrode. Formation of a thin film transistor (TFT) preferably comprising the gate electrode, amorphous silicon active regions and source and drain electrodes, is then completed on the insulating layer. To facilitate reduction of the number of masking steps needed to fabricate the display devices, a gate pad layer (e.g., indium tin oxide) is formed directly on the gate line by opening a window in the insulating layer and thereby eliminating an intermediate step (and associated masking step) of patterning the conductive material used to form the drain and source electrodes on the gate line before forming the gate pad layer. To inhibit formation of hillocks (and potential electrical "shorts" caused thereby) and minimize signal delays associated with the gate lines and electrodes, the gate lines and gate electrodes undergo a novel anodic oxidation step. In particular, the gate lines and gate electrodes are preferably formed to comprise a plurality of layers including an aluminum or related alloy first layer, a tantalum or related alloy second layer on the first layer and an anodic oxide containing tantalum (e.g., TaO5,) top layer.

Patent
23 Mar 1999
TL;DR: The floating-point adder as discussed by the authors performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients using a single functional unit.
Abstract: An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation. The floating-point adder permits all integer add, subtract and compare operations be performed by the floating-point adder without adding substantial additional hardware to the arithmetic logic unit.

Journal ArticleDOI
TL;DR: In a massive set of experiments with circuits whose optimal layout is not known, the microcanonical optimization algorithm, /spl mu/0, is able to match and even to improve, by as much as seven tracks, the best solutions known so far.
Abstract: This paper deals with the problem of linear gate assignment in two layout styles: one-dimensional logic array and gate matrix layout. The goal is to find the optimal sequencing of gates in order to minimize the required number of tracks, and thus to reduce the overall circuit layout area. This is known to be an NP-hard optimization problem, for which no absolute approximation algorithm exists. Here we report the use of a new optimization heuristic derived from statistical mechanics-the microcanonical optimization algorithm, /spl mu/0-to solve the linear gate assignment problem. Our numerical results show that /spl mu/0 compares favorably with at least five previously employed heuristics: simulated annealing, the unidirectional and the bidirectional Hong construction methods, and the artificial intelligence heuristics GM Plan and GM Learn. We also show how the algorithm is able to outperform microcanonical annealing. Moreover, in a massive set of experiments with circuits whose optimal layout is not known, our algorithm has been able to match and even to improve, by as much as seven tracks, the best solutions known so far.

Patent
03 Mar 1999
TL;DR: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the INSulator to form a gate conductor opening between the substrate and the insulators adjacent the trench, and forming a gate oxide and gate conductor in the gate-conducting opening as mentioned in this paper.
Abstract: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.

Patent
11 Jan 1999
TL;DR: In this article, a quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers was proposed, where a controllable-length quantum wire electron stub tuner is connected to the ring.
Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output. Setting the stub to a second length reverses the locations of the local maxima and minima, and the charge carriers propagate to the second output but not the first output. The invention can also include a second controllable-length stub attached to the ring to increase switching efficiency. A quantum switch according to the invention can also act as a simple binary NOT logic gate or a simple binary AND logic gate.

Journal Article
TL;DR: Reversible Energy Recovery Logic is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.
Abstract: We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme [1], which is a dualrail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-μm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal. key words: reversible logic, adiabatic circuit, clocked power

Journal ArticleDOI
TL;DR: In this paper, a combined flow over V-notch weir and below contracted rectangular gate was studied and analyzed and discharge equation was developed for both free and submerged gate flows.
Abstract: A combined flow over V-notch weir and below contracted rectangular gate was studied and analyzed. The study covered both free and submerged gate flow conditions, under different weir-gate dimensions. These dimensions include notch angle, notch height, gate width and gate height. The experimental data were analyzed and the roles of the different flow and weir-gate parameters are discussed. Based on dimensional analysis and using non-linear regression analysis, discharge equation was developed for both free and submerged gate flows. The developed equation consists of parameters for gate effect, weir effect and interference of the two devices. Equation showed good agreement with the experimental data and covers a wide range of weir-gate parameters and gate flow conditions.

Patent
06 Jul 1999
TL;DR: In this article, a flip-flop switch is driven depending on the state of a flipflop circuit, and a comparator outputs a first reset signal when an inductor current reaches the instruction value signal.
Abstract: A switch arranged between a DC power supply source and a load is driven depending on the state of a flip-flop circuit. An error amplifier outputs an instruction value signal determined based on an output voltage. A comparator outputs a first reset signal when an inductor current reaches the instruction value signal. An oscillator generates a set pulse. A first AND gate feeds as a second reset signal an AND-operation result between the Q-output of the flip-flop circuit and the first reset signal to the reset terminal of the flip-flop circuit and the negative logic input terminal of a second AND gate. The second AND gate feeds the set pulse to the set terminal of the flip-flop circuit according to the second reset signal.

Proceedings ArticleDOI
Reinaldo A. Bergamaschi1
01 Jun 1999
TL;DR: A novel internal model for synthesis is presented consisting of a novel RTL/gate-level network capable of representing all possible schedules that a given behavior may assume which allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.
Abstract: High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). Currently, this effect cannot be measured accurately because the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.

Patent
19 May 1999
TL;DR: In this article, one or more diodes are connected in a conductive path between the source and gate of a vertical MOSFET to prevent the voltage between the gate and source from exceeding a predetermined level and thereby protect the gate oxide layer from damage.
Abstract: One or more diodes are connected in a conductive path between the source and gate of a vertical MOSFET to prevent the voltage between the gate and source from exceeding a predetermined level and thereby protect the gate oxide layer from damage. The diodes are formed in the same polysilicon layer that is used to form the gate of the MOSFET, by implanting N and P-type dopants into the layer. To minimize the number of additional processing steps required, at least one of these implants is performed simultaneously with the implanting of the source or body of the MOSFET. As an additional aspect of the invention, the metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

Patent
17 Dec 1999
TL;DR: In this paper, an integrated circuit chip includes a domino logic gate, circuitry for selectively latching a logic output signal of the gate and an enable source for the gate, and the enable source and gate positions on the chip and a clock driving the chip has a frequency such that the enable signal arrives late at the logic gate during the evaluate phase of each clock cycle.
Abstract: An integrated circuit chip includes a domino logic gate, circuitry for selectively latching a logic output signal of the gate and an enable source for the gate. The enable source and gate positions on the chip and a clock driving the chip has a frequency such that the enable signal arrives late at the logic gate during the evaluate phase of each clock cycle. The circuitry for selectively latching is constructed so that the domino logic gate is evaluated or latched during the same clock cycle that the enable signal is derived despite the aforementioned positions and frequency.

Patent
William C. Saxman1
09 Jul 1999
TL;DR: In this paper, a bit breaker is formed of a U-shaped base and latchable gate which closes the U. When the gate is in a closed position, evenly spaced chocks on both the base and gate protrude into the central cavity of the bit breaker to engage slots formed in the bit.
Abstract: A bit breaker is formed of a U-shaped base and latchable gate which closes the U. When the gate is in a closed position, evenly spaced chocks on both the base and gate protrude into the central cavity of the bit breaker to engage slots formed in the bit. The bit breaker is designed to be used with either roller cone bits or drag bits.

Proceedings ArticleDOI
07 Nov 1999
TL;DR: An approach for automated synthesis of globally DI and locally SI circuits is presented, based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used.
Abstract: Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.

Patent
16 Aug 1999
TL;DR: In this article, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship.
Abstract: In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.

Proceedings ArticleDOI
14 Jun 1999
TL;DR: In this article, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.
Abstract: Direct tunneling of ultra-thin gate oxides results in exponential increases in gate leakage current (Lo et al, 1997). Moreover, the loss of inversion charge due to the carrier quantization then becomes significant. Hence, more physically accurate models are urgently needed. In this paper, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.