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Showing papers on "AND gate published in 2004"


Journal ArticleDOI
TL;DR: A general polymeric design of fluorescent logic gates, for example, AND, is illustrated, using temperature and pH as inputs.
Abstract: We illustrate a general polymeric design of fluorescent logic gates, for example, AND, using temperature and pH as inputs.

305 citations


Journal ArticleDOI
TL;DR: In this paper, the authors give quantum circuits that simulate an arbitrary two-qubit unitary operator up to a global phase, and prove that gate counts are optimal in the worst and average cases.
Abstract: We give quantum circuits that simulate an arbitrary two-qubit unitary operator up to a global phase. For several quantum gate libraries we prove that gate counts are optimal in the worst and average cases. Our lower and upper bounds compare favorably to previously published results. Temporary storage is not used because it tends to be expensive in physical implementations. For each gate library, the best gate counts can be achieved by a single universal circuit. To compute the gate parameters in universal circuits, we use only closed-form algebraic expressions, and in particular do not rely on matrix exponentials. Our algorithm has been coded in $\mathrm{C}++$.

197 citations


Patent
10 Feb 2004
TL;DR: In this article, a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation is described.
Abstract: A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

172 citations


Journal ArticleDOI
TL;DR: A molecule-based binary half-adder with optical inputs and outputs has been demonstrated, capable of carrying out all mathematical operations necessary for digital computing.
Abstract: A molecule-based binary half-adder with optical inputs and outputs has been demonstrated. The half-adder consists of two photochromic organic molecules in solution and a third-harmonic-generating crystal. One substance acts as an AND Boolean logic gate and the other as an XOR gate. Inputs are laser pulses at 1064 or 532 nm that initiate photoisomerization reactions. Outputs are the optical absorbance of a fullerene radical anion (AND gate) and fluorescence of a porphyrin (XOR gate). The system carries out binary addition based on the laser input pulses. Half-adders in combination are capable of carrying out all mathematical operations necessary for digital computing.

161 citations


Journal ArticleDOI
TL;DR: An all-optical logical AND gate at 10 Gbit/s based on cross-gain modulation (XGM) in two cascaded semiconductor optical amplifiers (SOAs) is demonstrated.
Abstract: An all-optical logical AND gate at 10 Gbit/s based on cross-gain modulation (XGM) in two cascaded semiconductor optical amplifiers (SOAs) is demonstrated. Single-port-coupled SOAs are employed and specially designed to improve the output extinction ratio as well as the output performance of the logic operation. The output signal power and extinction ratio from the first-stage wavelength converter are critical to achieving all-optical logical AND operation.

133 citations


Patent
28 Oct 2004
TL;DR: In this article, the problem of providing a semiconductor device having a structure capable of sufficiently increasing gate breakdown voltage, even in the semiconductor devices in which a number of transistor cells having a trench structure are formed in a matrix shape, and gate wiring composed of a metal film is in contact with the gate electrodes of the transistors.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure capable of sufficiently increasing gate breakdown voltage, even in the semiconductor device in which a number of transistor cells having a trench structure are formed in a matrix shape, and gate wiring composed of a metal film is in contact with the gate electrodes of the transistors.SOLUTION: A semiconductor device comprises a cell region 10 in which transistor cells are arranged in a matrix shape. Each transistor cell has a trench structure in which recessed grooves 11 are formed in a semiconductor layer 1, a gate insulating film 4 is formed in the recessed grooves 11, and gate electrodes 5 composed of, for example, polysilicon are provided in the narrow groves 11. In order to contact a gate wiring 9 composed of a metal film, a gate pad 5a, which is successively provided with the gate electrodes 5, is formed in a recessed part 12 simultaneously provided with the recessed grooves 11.

117 citations


Patent
26 Feb 2004
TL;DR: In this article, an apparatus is provided which integrates sensor functionality with an active matrix display such as an AMLCD, where a conventional active matrix 6 of LCD pixels is provided with standard display source and gate drivers 4 and 5.
Abstract: An apparatus is provided which integrates sensor functionality with an active matrix display such as an AMLCD. A conventional active matrix 6 of LCD pixels 10 is provided with standard display source and gate drivers 4 and 5. The display source driver 4 supplies data signals for generating the required pixel response to column electrodes 12 which are also connected to an output arrangement 19 including sense amplifiers 20. During a display phase of operation, the AMLCD operates conventionally with the matrix 6 being refreshed a row at a time and frame by frame. Between frames, the sense amplifiers 20 are enabled and the matrix 6 is again scanned by the gate driver 5. The characteristics of each pixel represent an external stimulus, the pixel generating a sensor signal sensed by the relevant sense amplifier 20 and supplied at an output 23 of the arrangement.

110 citations


Journal ArticleDOI
TL;DR: In this article, a hierarchy of tunneling models suitable for the two-and three-dimensional simulation of logic and nonvolatile semiconductor memory devices is presented, where the crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, and the modelling of static and transient defect-assisted tunneling.
Abstract: We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices.

98 citations


Journal ArticleDOI
TL;DR: In this article, the first successful integration of two independent gates on a p-type FinFET was presented, to the best of our knowledge, which represents a significant performance improvement over previously reported Independent-Gate Fin-FET results.
Abstract: We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 /spl mu/m, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.

82 citations


Patent
28 Sep 2004
TL;DR: In this paper, a pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor, which can act as both a leaking transistor and either a transfer gate or a reset gate.
Abstract: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may be a separate and individual transistor having the gate profile of a transfer gate or a reset gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor, adjusting the channel length of the transistor, or thinning the gate oxide on the transistor. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.

80 citations


Patent
09 Jun 2004
TL;DR: One-time programmable, non-volatile field effect devices and methods of making same are discussed in this article, where an electromechanically-deflectable, nanotube switching element is electrically coupled to one of the source, drain and gate.
Abstract: One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate has a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically coupled to one of the source, drain and gate and has an electromechanically-deflectable nanotube element that is positioned to be deflectable in response to electrical stimulation to form a non-volatile closed electrical state between the one of the source, drain and gate and its corresponding terminal.

Journal ArticleDOI
TL;DR: In this article, the material requirements for metal gate CMOS technology and the challenges involved in the integration of metal gate electrodes in a nanoscale transistor are discussed, including the choice of metal-gate materials for conventional bulk and advanced transistor structures, the physics of the metal-dielectric interface, and the process integration of these materials in a CMOS process.

Proceedings ArticleDOI
13 Dec 2004
TL;DR: In this paper, the authors investigated the electronic transport in multiple-gate devices at the ultimate cross-section channel limit by modeling ballistic nanowire MOSFET architectures and compared the electrical performances of these structures as a function of their equivalent gate number and gate configuration.
Abstract: The electronic transport in multiple-gate devices is theoretically investigated at ultimate cross-section channel limit by modeling ballistic nanowire MOSFET architectures. The electrical performances of these structures are compared as a function of their "equivalent gate number" and gate configuration. In this approach, the 3D Schrodinger-Poisson system is self-consistently solved and the ballistic transport is treated with the nonequilibrium Green's function formalism.

Patent
25 Mar 2004
TL;DR: In this paper, the first and second data paths are coupled to a logic circuit for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal.
Abstract: A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Patent
25 May 2004
TL;DR: In this paper, a method and apparatus for forming a nitrided gate dielectric layer using a smooth-varying modulated RF power source to reduce electron temperature spike is presented.
Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.

Patent
22 Jan 2004
TL;DR: In this paper, a gate field effect transistor (GFET) with nitrogen in the interface of the gate insulation film was proposed to prevent diffusion of boron from source and drain part 208.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a highly reliable insulated gate transistor with small dispersion, excellent in transistor characteristic even in a short-gate PMOS transistor. SOLUTION: This semiconductor device includes nitrogen in a gate insulation film 205 of an insulated gate field effect transistor formed in a region of width less than 1.5 μm in the length direction of the gate, and in the interface between a semiconductor substrate 201 and the gate insulation film 205. The concentration of nitrogen included in the interface of the gate insulation film 205 is more than 1×1020 (/cm3), and it also includes a halogen element. Nitrogen in the interface between the semiconductor substrate 201 and the gate insulation film 205 prevents diffusion of boron from source and drain part 208 to suppress abnormal diffusion of boron, and simultaneously, the halogen element in the gate insulation film 205 serves to prevent the degradation of the characteristic of the interface of a channel and gate insulation film.

Journal ArticleDOI
TL;DR: An all-optical system for the addition of binary numbers is proposed in which input binary digits are encoded by appropriate cells in two different planes and outputbinary digits are expressed as the presence or the absence of a light signal.
Abstract: An all-optical system for the addition of binary numbers is proposed in which input binary digits are encoded by appropriate cells in two different planes and output binary digits are expressed as the presence (=1) or the absence (=0) of a light signal. The intensity-based optical XOR and AND logic operations are used here as basic building blocks. Nonlinear materials, appropriate cells (pixels), and other conventional optics are utilized in this system.

Patent
Won-Ho Cho1, Gyoo-Chul Jo2, Gue-Tai Lee1, Jin-Gyu Kang1, Beung-Ilwa Jeong1, Kim Jin Young1 
25 Jun 2004
TL;DR: In this article, the authors present an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate.
Abstract: The present invention is an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal is one of aluminum and aluminum alloy; a gate insulation layer on the substrate covering the gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer perpendicularly crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad on the gate insulation layer, wherein the data line, the source and drain electrode and the data pad have a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper; a passivation layer formed on the gate insulation layer to cover the data line, source and drain electrodes, and data pad, wherein the passivation layer has a drain contact hole exposing a portion of the drain electrode, a gate pad contact hole exposing a portion of the gate pad, and a data pad contact hole exposing a portion of the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer, all of which are formed of a transparent conductive material on the passivation layer.

Journal ArticleDOI
TL;DR: In this paper, a cross-gain modulation of optical amplifiers was used to achieve a 10 Gb/s all-optical AND gate using the first SOA with signal B and clock injection.
Abstract: By using the cross-gain modulation of semiconductor optical amplifiers (SOAs), a novel all-optical AND gate has been successfully demonstrated at 10 Gb/s. Firstly, Boolean \overlineB was obtained using the first SOA with signal B and clock injection. Then, the all-optical AND gate is achieved by simultaneously injecting signal A and signal \overlineB out of the first SOA.

Proceedings ArticleDOI
22 Mar 2004
TL;DR: It is found that increasing threshold voltage improves the SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses.
Abstract: Due to technology scaling, smaller devices and lower operating voltages, next generation circuits are highly susceptible to soft errors. Another important problem confronting silicon scaling is static power consumption. In this paper, we analyze the effect of increasing threshold voltage (widely used for reducing static power consumption) on the soft error rate (SER). We find that increasing threshold voltage improves the SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that clever use of high V/sub t/ can improve the robustness of 6T-SRAMs.

Journal ArticleDOI
TL;DR: Two digit-serial architectures for normal basis multipliers over (GF(2m)) have the same gate count and gate delay and an algorithm that can considerably reduce the redundancy is developed.
Abstract: In this article, two digit-serial architectures for normal basis multipliers over (GF(2m)) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and time complexities.

Proceedings ArticleDOI
13 Dec 2004
TL;DR: In this paper, the use of a metal gate/high-k stack offers improved mobility over polysilicon/highk gates stacks while maintaining decreased gate leakage compared to conventional SiO/sub 2/ stacks, thus allowing high performance transistor scaling to continue.
Abstract: For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared to conventional SiO/sub 2/ stacks, thus allowing high-performance transistor scaling to continue.

Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this article, a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate is presented, which is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement.
Abstract: This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

Proceedings ArticleDOI
16 Aug 2004
TL;DR: This paper presents a quantum dot cellular automata complex gate composed from simple 3-input majority gates that can be configured into many useful gate structures such as a 4-input and gate, a product of sums representation, a sum of products representation, and other variations.
Abstract: This paper presents a quantum dot cellular automata complex gate composed from simple 3-input majority gates. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, a product of sums representation, a sum of products representation, and other variations.

Journal ArticleDOI
TL;DR: In this article, a class of downstream-water-level feedback canal controllers was described, and several controllers within this class were tuned with the same quadratic performance criteria (i.e., identical penalty functions for optimization).
Abstract: In a companion paper, a class of downstream-water-level feedback canal controllers was described. Within this class, a particular controller is chosen by selecting which controller coefficients to optimize (tune), the remaining coefficients being set to zero. These controllers range from a series of simple proportional-integral (PI) controllers to a single centralized controller that considers lag times. In this paper, several controllers within this class were tuned with the same quadratic performance criteria (i.e., identical penalty functions for optimization). The resulting controllers were then tested through unsteady-flow simulation with the ASCE canal automation test cases for canal 1. Differences between canal and gate properties, as simulated and as assumed for tuning, reduced controller performance in terms of both water-level errors and gate movements. The test case restrictions placed on minimum gate movement caused water levels to oscillate around their set points. This resulted in steady-state errors and much more gate movement (hunting). More centralized controllers handle unscheduled flow changes better than a series of local PI controllers. Controllers that explicitly account for pool wave travel times did not improve control as much as expected. Sending control actions within a given pool to upstream pools improved performance, but caused oscillations in some cases, unless control signals were also sent downstream. A good compromise between controller performance and complexity is provided by controllers that pass feedback from a given water level to the check structure at the upstream end of its pool (i.e., that used for downstream control of an individual pool) and to all upstream and one downstream check structures.

Proceedings ArticleDOI
04 Oct 2004
TL;DR: In this article, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated and it is shown that in scaled devices, fringing capacitance dominates the effective gating capacitance.
Abstract: In this paper, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated. It is shown that in scaled devices, fringing capacitance dominates the effective gate capacitance. Hence with optimum underlap the effective gate capacitance can be reduced thereby reducing the delay and power. Gate underlapping also reduces gate direct tunneling current in the off-state.

Patent
15 Dec 2004
TL;DR: In this article, a novel image sensor cell structure and method of manufacture is presented, which comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectrics layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of another conductivity layer atop the collection well at the substrate surface, and a diffusion region of a second side of a gate conductor forming a channel region between the collector well layer and the diffusion region.
Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

Book ChapterDOI
01 Jan 2004
TL;DR: This chapter examines probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF), which can dynamically adapt to structural and signal-based faults.
Abstract: As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.

Patent
Tobita Youichi1
15 Apr 2004
TL;DR: In this paper, a deactivation transition detect circuit detects transition of a selected gate line from a selected state to a non-selected state in the gate lines and an operation related to data writing in the next cycle is started in accordance with the deactivation signal detecting the transition.
Abstract: Pixels are arranged in rows and columns and gate lines are arranged corresponding to the rows of pixels in a display panel. Deactivation transition detect circuit detects transition of a selected gate line from a selected state to a non-selected state in the gate lines. An operation related to data writing in the next cycle is started in accordance with a deactivation transition detect signal detecting the transition. In an active matrix type display device, a write margin for data writing of the next cycle is increased when a selected gate line transits to a non-selected state.

Journal ArticleDOI
TL;DR: In this article, the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling and the limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device.
Abstract: Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.