Showing papers on "AND gate published in 2006"

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

Abstract: A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.

Apparatus and method for driving liquid crystal display device

Abstract: An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Communicating chemical congregation: a molecular AND logic gate with three chemical inputs as a "lab-on-a-molecule" prototype.

Abstract: We demonstrate the first three-input molecular AND logic gate based on three chemical inputs as a direct way of detecting congregations of chemical species. The AND gate operates in water and responds to Na+, H+, and Zn2+ inputs with an enhanced fluorescence signal when pre-set concentration thresholds are exceeded. Future “lab-on-a-molecule” devices could have application in medicine for rapid disease screening.

Ultrafast integrable and reconfigurable XNOR, AND, NOR, and NOT photonic logic gate

Abstract: A novel, simple, compact, and integrable scheme of reconfigurable and ultrafast photonic logic gate is demonstrated, based on a single semiconductor optical amplifier (SOA) and able to process ultrafast signals. XNOR function has been optically implemented exploiting four-wave mixing and cross-gain modulation in an SOA. The same scheme can be easily reconfigured to obtain AND, NOR, and NOT logic gates. Performances in terms of bit error rate for 20-ps return-to-zero signals at 10 Gb/s show a power penalty limited to 0.5 dB for all logic gates but the AND, which experiences regeneration (-2-dB power penalty) due to nonlinear SOA noise compression.

Long-range three-dimensional imaging using range-gated laser radar images

Abstract: An approach to long-range 3-D imaging using laser illuminated range-gated viewing is presented. The basis for 3-D scene reconstruction is an image sequence acquired using a sliding gate delay time. Two different methods are suggested, and algorithm performance is investigated through Monte Carlo simulations using a simplified system and imaging model. Assumptions are justified by comparison with real measurements at range of 0.8 to 7.2 km. It is shown that range resolution and precision become significantly better than system design parameters such as gate length, gate transition length, and gate step length. The presented reconstruction methods thus enable high-precision range imaging using available long-range gated imaging systems.

High-contrast light-by-light switching and AND gate based on nonlinear photonic crystals

Abstract: We present a light-by-light photonic crystal configuration consisting of a bent waveguide with three embedded Kerr-type nonlinear rods and a T-branch waveguide. We show that such a configuration can also demonstrate all-optical AND gate operation with extremely high contrast between the OFF state and the ON state in its transmission. The photonic crystal configuration of all-optical light-by-light switching is simple and thus facilitates the fabrication of practical all-optical devices and further large-scale optical integration.

Performance of a spin-based insulated gate field effect transistor

Abstract: Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies, and smaller source-drain leakage currents.

Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs

Abstract: Compact-modeling principles and solutions for nanoscale double-gate and gate-all-around MOSFETs are explained The main challenges of compact modeling for these devices are addressed, and different approaches for describing the electrostatics, the transport mechanisms, and the high-frequency behavior are explained Several approximations used to derive analytical solutions of Poisson's equation for doped and undoped devices are discussed, and the need for self-consistency with Schrodinger's equation and with the current continuity equation resulting from the transport models is addressed Several techniques to extend the compact modeling to the high-frequency regime and to study the RF performance, including noise, are presented and discussed

Gate-length biasing for runtime-leakage control

Abstract: Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20/spl times/. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized. The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage. Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

Overlapping rules and logic variables in functional logic programs

Abstract: Functional logic languages extend purely functional languages with two features: operations defined by overlapping rules and logic variables in both defining rules and expressions to evaluate. In this paper, we show that only one of these features is sufficient in a core language. On the one hand, overlapping rules can be eliminated by introducing logic variables in rules. On the other hand, logic variables can be eliminated by introducing operations defined by overlapping rules. The proposed transformations between different classes of programs not only give a better understanding of the features of functional logic programs but also may simplify implementations of functional logic languages.

Experimental observation of a 1.5 μm band wavelength conversion and logic NOT gate at 40 Gbit/s based on sum-frequency generation

Abstract: We have experimentally verified a new idea for 40 Gbit/s wavelength conversion within the 1.5 μm band based on sum-frequency generation (SFG) in a periodically poled LiNbO3 waveguide. The spectrum and the temporal waveform of the output pump reveal that the input cw pump is converted to an optical pulse during SFG. Not only wavelength conversion but also a logic NOT gate at 40 Gbit/s are experimentally observed.

All-optical AND gate with improved extinction ratio using signal induced nonlinearities in a bulk semiconductor optical amplifier

Abstract: An all-optical AND gate based on optically induced nonlinear polarization rotation of a probe light in a bulk semiconductor optical amplifier is realized at a bit rate of 2.5Gbit/s. By operating the AND gate in an up and inverted wavelength conversion scheme, the extinction ratio is improved by 8dB compared with previously published work.

All-optical AND and NAND gates based on cascaded second-order nonlinear processes in a Ti-diffused periodically poled LiNbO(3) waveguide.

Abstract: All-optical AND and NAND gates have been demonstrated in a Ti-diffused periodically poled LiNbO3 channel waveguide which has two second-harmonic phase-matching peaks by cascaded sum-frequency-generation/difference-frequency-generation (cSFG/DFG) and sum-frequency-generation (SFG) processes. The conversion efficiency of signal to idler (AND gate signal) was approximately 0 dB in cSFG/DFG process. In the second SFG process, more than 15 dB extinction ratio between signal and dropped signal (NAND gate signal) has been observed.

Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics

Abstract: In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO/sub 2/. Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content.

All-optical half adder using an SOA and a PPLN waveguide for signal processing in optical networks.

Abstract: We demonstrate an all-optical half adder for bit-wise addition of two serial data streams that simultaneously generates Sum and Carry outputs. The module performs the required XOR and AND operations using only two nonlinear optical elements. Difference Frequency Generation in a periodically poled lithium niobate waveguide serves as the AND gate and cross-gain modulation in a semiconductor optical amplifier is employed to generate the XOR output. Error free operation for RZ data is reported.

In-service reconfigurable DRAM and flash memory device

Abstract: A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model -- in posynomial form -- is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual- VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach.

Spin MOSFETs as a basis for spintronics

Abstract: This article reviews a recently proposed new class of spin transistors referred to as spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs), and their integrated circuit applications. The fundamental device structures, operating principle, and theoretically predicted device performance are presented. Spin MOSFETs potentially exhibit significant magnetotransport effects, such as large magneto-current, and also satisfy important requirements for integrated circuit applications such as high transconductance, low power-delay product, and low off-current. Since spin MOSFETs can perform signal processing and logic operations and can store digital data using both charge transport and spin degrees of freedom, they are expected to be building blocks for memory cells and logic gates in spin-electronic integrated circuits. Novel spin-electronic integrated circuit architectures for nonvolatile memory and reconfigurable logic employing spin MOSFETs are also presented.

Liquid crystal display and method of driving the same

Abstract: A liquid crystal display (LCD) and a method for driving the same are provided. The LCD includes a liquid crystal panel divided into a plurality of panel regions having data lines and gate lines arranged two-dimensionally; gate drivers that correspond to the panel regions, are independently driven, and alternately supply gate signals to the corresponding panel regions; a data driver supplying data signals to the data lines; and a backlight unit radiating light to the liquid crystal panel. Accordingly, color mixing can be substantially prevented by changing the transmission mode of gate signals.

A method to determine the gate bias-dependent and gate bias-independent components of MOSFET series resistance from S-parameters

Abstract: An S-parameter measurement-based procedure for the extraction of the bias dependent and bias independent components of the MOSFET series resistance is presented. The proposed procedure allows the direct and analytical determination of these components from measurements performed on a single device. The method is verified by achieving good agreement between simulated and experimental data for a 0.18-/spl mu/m channel-length MOSFET.

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Abstract: Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

ESD protection device and method

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Quantum phase gate in an optical cavity with atomic cloud

Abstract: We propose a scheme for implementing a two-qubit quantum phase gate for intracavity fields. In the scheme, two qubits are encoded in zero- and one-photon Fock states of two intracavity modes, and a four-level $\mathsf{N}$-type atomic ensemble trapped in a cavity mediates the conditional phase gate within a given interaction time. We also discuss the influence of the atomic spontaneous emission and the decay of the cavity modes on the photon loss and gate fidelity, showing the scheme is within the current experiment technology.

Tft substrate, reflective tft substrate, and method of manufacturing same

Abstract: PROBLEM TO BE SOLVED: To propose a TFT substrate, a reflective TFT substrate, and a method of manufacturing the same which can enable stable operations for an extended period of time, prevent crosstalk, and remarkably reduce the manufacturing cost by reducing the number of steps in a manufacturing process. SOLUTION: A reflective TFT substrate 1a comprises a glass substrate 10, a gate electrode 23 and gate wiring 24 which are insulated by a gate insulating film 30 covering the top surfaces of the gate electrode 23 and the gate wiring 24 and an interlayer insulating film 50 covering the sides of the gate electrode 23 and the gate wiring 24, an n-type oxide semiconductor layer 40 formed on the gate insulating film 30 on the gate electrode 23, a reflective metal layer 60a formed on the n-type oxide semiconductor layer 40 via a channel portion 44, and a channel guard 500 for protecting the channel portion 44. COPYRIGHT: (C)2008,JPO&INPIT

Circuit design issues in multi-gate FET CMOS technologies

Abstract: Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

Demonstration and dynamic analysis of trapping of hot electrons at gate edge model for current collapse and gate lag in GaN-based high-electron-mobility transistor including self-heating effect

Abstract: Using a two-dimensional simulator, the authors report on demonstration of trapping of hot electrons at gate edge model in GaN-based high-electron-mobility transistors. Dynamic picture of hot electrons under gate pulse voltage is discussed in detail. Trapped charges may accumulate under punch-off gate voltage at gate edge drain side, where the electric field significantly changes and gate-voltage-dependent strain is induced. Significant band barrier is formed at the gate edges causing a notable current collapse. Self-heating effect is one of the reasons for current collapse and gate lag.

Statistical Timing Yield Optimization by Gate Sizing

Abstract: In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30% on the average, over deterministic timing optimization for at most 10% area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for iso-area solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13-mum technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Abstract: Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on the gate input state, and a good input vector is able to minimize the leakage when the circuit is in the sleep mode. The gate replacement technique is a very effective method to further reduce the leakage current. In this paper, we propose a fast algorithm to find a low leakage input vector with simultaneous gate replacement. Results on MCNC91 benchmark circuits show that our algorithm produces $14 %$ better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm. In particular, the average runtime for the ten largest combinational circuits has been dramatically reduced from 1879 seconds to 0.34 seconds.