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Showing papers on "AND gate published in 2007"


Journal ArticleDOI
TL;DR: A synthetic AND gate in the bacterium Escherichia coli is constructed that integrates information from two promoters as inputs and activates a promoter output only when both input promoters are transcriptionally active.
Abstract: Microorganisms use genetic circuits to integrate environmental information. We have constructed a synthetic AND gate in the bacterium Escherichia coli that integrates information from two promoters as inputs and activates a promoter output only when both input promoters are transcriptionally active. The integration occurs via an interaction between an mRNA and tRNA. The first promoter controls the transcription of a T7 RNA polymerase gene with two internal amber stop codons blocking translation. The second promoter controls the amber suppressor tRNA supD. When both components are transcribed, T7 RNA polymerase is synthesized and this in turn activates a T7 promoter. Because inputs and outputs are promoters, the design is modular; that is, it can be reconnected to integrate different input signals and the output can be used to drive different cellular responses. We demonstrate this modularity by wiring the gate to integrate natural promoters (responding to Mg2+ and AI-1) and using it to implement a phenotypic output (invasion of mammalian cells). A mathematical model of the transfer function is derived and parameterized using experimental data.

399 citations


Book
09 Mar 2007
TL;DR: Evaluation and Logic Models: Using the Logic Model to provide Technical Assistance and Challenges in Developing Logic Models.
Abstract: List of Figures. Preface. 1. Evaluation and Logic Models. 2. The Uses of Logic Models. 3. The Components of a Logic Model. 4. The Connections in a Logic Model. 5. Developing Logic Models to Support Evaluation. 6. Developing Logic Models of Differing Complexity. 7. Using a Logic Model to Identify Evaluation Questions. 8. Using a Logic Model to Support Explanatory Evaluation. 9. Challenges in Developing Logic Models. 10. Developing Logic Models for Complex Projects. 11. Using Logic Models to Evaluate a Family of Projects. 12. Using the Logic Model to Provide Technical Assistance. Appendix: The Phases of an Evaluation. About the Author. Glossary. References.

155 citations


Patent
Kyoung-Ho Kim1, Seong Jin Jang1
01 Mar 2007
TL;DR: In this paper, a circuit and method for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device is presented, where the output node disposed for receiving a signal indicative of an input or output operation, and the gate node in signal communication with a gate of the local from/to global input multiplexer for providing a gate signal of a first or second level in the presence of the output operation.
Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

130 citations


Journal ArticleDOI
TL;DR: In this paper, the geometry-dependent parasitic components in multifin double-gate fin field effect transistors (FinFETs) are modeled as functions of gate geometry parameters using a conformal mapping method.
Abstract: This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied

122 citations


Journal ArticleDOI
TL;DR: This study presents a novel design for QCA cells and another possible and unconventional scheme for majority gates and proves that how this reduction method decreases gate counts and levels in comparison to the other previous methods.
Abstract: Quantum-dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the nano-scale. The basic Boolean primitive in QCA is the majority gate. In this study we present a novel design for QCA cells and another possible and unconventional scheme for majority gates. By applying these items, the hardware requirements for a QCA design can be reduced and circuits can be simpler in level and gate counts. As an example, a one bit QCA adder is constructed by applying our new scheme. Beside, we prove that how our reduction method decreases gate counts and levels in comparison to the other previous methods.

101 citations


Journal ArticleDOI
TL;DR: The reported pressure sensors based on completely flexible organic thin film transistors show potential advantages of flexibility of the structure, low cost and versatility of the device structure for sensor technologies, and a reversible dependence of the current on the pressure.

84 citations


Journal ArticleDOI
TL;DR: In this paper, a 2D self-consistent Schrodinger-Poisson solver has been implemented to simulate the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs.
Abstract: In this paper, simulation-based research on the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs is carried out. To do so, a 2-D self-consistent Schrodinger-Poisson solver has been implemented. The inclusion of the quantum effects has been demonstrated to be necessary for the accurate simulation of these devices in the nanometer range. Specifically, this paper is focused on the corner effects in multiple-gate SOI MOSFETs, defined as the formation of independent channels with different threshold voltages. Corner effects are studied as a function of different parameters, such as the doping density, silicon-fin dimensions, corner rounding, and gate oxide thickness. Finally, the relation between corner effects and the transition from a fully to a partially depleted body is analyzed.

84 citations


Journal ArticleDOI
TL;DR: In this paper, the impact of high-k gate dielectrics on device short-channel and circuit performance of fin field effect transistors is studied over a wide range of dielectric permittivities.
Abstract: The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance Cof in addition to an increase in the internal fringe capacitance Cif with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering

83 citations


Journal ArticleDOI
TL;DR: In this paper, the buck-boost Z-source power conversion concept is integrated into the current source (CS) inverter topology to develop single and three-phase z-source CS inverters.
Abstract: Traditionally, current source (CS) inverters have been adopted for use in medium and high power industry applications. These inverters, however, support only current-buck dc-ac power conversion and need a relatively complex modulator, as compared to conventional voltage source (VS) inverters. To address these limitations, this paper presents an integration of the buck-boost Z-source power conversion concept to the CS inverter topology to develop single- and three-phase Z-source CS inverters. For their efficient control, the paper starts by evaluating different carrier-based reference formulations to identify different inverter state placement possibilities. The paper then proceeds to design appropriate "reference-to-switch" assignments or logic equations for mapping out the correct CS gating signals, allowing a simple carrier-based modulator to control a Z-source CS inverter with complications such as commutation difficulties and "many-to-many" state assignments readily resolved. The developed system can be implemented using a digital signal processor with an embedded VS pulse-width modulator and an external programmable logic device, hence offering a competitive solution for medium power single and three-phase buck-boost power conversion. Theory, simulation, and experimental results are presented in the paper

74 citations


Journal ArticleDOI
Tad Hogg1, Greg Snider1
TL;DR: This work identifies reliability thresholds in the ability of defective crossbars to implement boolean logic, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components.
Abstract: Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.

62 citations


Patent
11 Jan 2007
TL;DR: In this paper, an array substrate device includes a gate line formed on a substrate extending along a first direction having a gate electrode, a data line forming along a second direction, having a data pad disposed apart from a first end of the data line, the data and gate lines defining a pixel region, a gate pad formed on the substrate disposed away from the gate line, a thin film transistor formed at a crossing region of the gate and data lines and including the gate electrode.
Abstract: An array substrate device includes a gate line formed on a substrate extending along a first direction having a gate electrode, a data line formed on the substrate extending along a second direction having a data pad disposed apart from a first end of the data line, the data and gate lines defining a pixel region, a gate pad formed on the substrate disposed apart from a first end of the gate line, a thin film transistor formed at a crossing region of the gate and data lines and including the gate electrode, a semiconductor layer, a source electrode, and a drain electrode, a black matrix overlapping the thin film transistor, the gate line, and the data line except for a first portion of the drain electrode, a first pixel electrode at the pixel region contacting the first portion of the drain electrode and the substrate, a color filter on the first pixel electrode at the pixel region, and a second pixel electrode on the color filter contacting the first pixel electrode.

Patent
24 May 2007
TL;DR: In this article, a logic element includes memory elements, multiplexers, and controls, which are arranged in levels including a highest level with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexer and at least one output.
Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Patent
27 Apr 2007
TL;DR: In this article, an image display device of reduced cost is presented, which consists of a plurality of gate lines, signal lines, and thin-film transistors on an insulating substrate.
Abstract: An image display device of reduced cost is provided. A plurality of gate lines, a plurality of signal lines formed to cross the gate lines in a matrix fashion, and a plurality of thin-film transistors are formed on an insulating substrate, and the plurality of gate lines are laminated electrodes. The plurality of thin-film transistors are configured of transistors of two types of an n-channel conductivity type and a p-channel conductivity type. Gate electrodes of thin-film transistors of one type are laminated electrodes of the same configuration as the gate lines, and gate electrodes of thin-film transistors of the other type are configured of electrodes of the same layer as bottom electrodes of the gate lines.

Patent
02 May 2007
TL;DR: In this paper, a liquid crystal display (LCD) and a method for driving the same are provided. But the authors do not consider the effect of color mixing on the performance of the display.
Abstract: A liquid crystal display (LCD) and a method for driving the same are provided. The LCD includes a liquid crystal panel divided into a plurality of panel regions having data lines and gate lines arranged two-dimensionally; gate drivers that correspond to the panel regions, are independently driven, and alternately supply gate signals to the corresponding panel regions; a data driver supplying data signals to the data lines; and a backlight unit radiating light to the liquid crystal panel. Accordingly, color mixing can be substantially prevented by changing the transmission mode of gate signals.

Journal ArticleDOI
TL;DR: In this paper, an all-optical bit-wise 3-input AND gate using a single periodically-poled-lithium-niobate (PPLN) waveguide as a nonlinear optical element was demonstrated.
Abstract: Demonstrated is an all-optical bit-wise 3-input AND gate using a single periodically-poled-lithium-niobate (PPLN) waveguide as a nonlinear optical element. The module generates output ' 1' bits only when all inputs are '1', with negligible power penalty.

Journal ArticleDOI
TL;DR: The proposed methodology provides a powerful tool for technologists to optimize the gate stack and fin-patterning processes and provides a simple model to capture the anisotropy of mobility in device and circuit simulators.
Abstract: In this paper, we propose a simple methodology for the extraction of the top and sidewall mobility in FinFET like triple-gate device architectures. The underlying assumptions are outlined and verified by simulations and experiments. Using this model, the top and sidewall mobility on both n- and p-channel FinFETs, fabricated with various fin-patterning processes and gate dielectrics, was extracted. It is shown that the choice of the hard mask and corner-rounding processes and the gate dielectric impacts the top and sidewall mobility differently. The proposed methodology provides a powerful tool for technologists to optimize the gate stack and fin-patterning processes. It also provides a simple model to capture the anisotropy of mobility in device and circuit simulators

Journal ArticleDOI
TL;DR: The design of two logic gates, a biological AND and a biological XOR, can be combined to produce a half-adder, one of the fundamental elements of complex systems engineering, and represent a promising basis for the design of more complex genetic circuits.
Abstract: The building of complex systems from basic logic gates is one of the hallmarks of circuit design in electrical engineering. The question arises whether a similar strategy can be adopted for the design of artificial biological systems. In this paper, we present the design of two logic gates, a biological AND and a biological XOR. They can be combined to produce a half-adder, one of the fundamental elements of complex systems engineering, and represent a promising basis for the design of more complex genetic circuits. Design space exploration allowed us to screen gate variants, while sensitivity analysis of refined models contributed to the specific implementation of the gates at the DNA level. The XOR gate is based on two specific proteases, which reciprocally inactivate co-synthesised transcription factors. The AND gate is designed such that, in the presence of two signals, a tRNA suppresses the premature termination of T7 RNA polymerase translation. Computer models confirmed that both designs allow gate behaviour that is reasonably close to idealised gates.

Patent
09 Oct 2007
TL;DR: In this article, an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay).
Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Proceedings Article
06 Jan 2007
TL;DR: In this paper, a simple extension of LTL is proposed, which is called N-LTL, that allows non-monotonic specification of goals, and properties of N- LTL are studied.
Abstract: One of the main ways to specify goals of agents is to use temporal logics. Most existing temporal logics are monotonic. However, in representing goals of agents, we often require that goals be changed non-monotonically. For example, the initial goal of the agent may be to be always in states where p is true. The agent may later realize that under certain conditions (exceptions) it is ok to be in states where p is not true. In this paper, we propose a simple extension of LTL, which we call N-LTL, that allows non-monotonic specification of goals. We study properties of N-LTL. We also consider a translation from N-LTL to logic programs and study the relationship between N-LTL and logic programs.

Journal ArticleDOI
TL;DR: It is shown that the derandomized evolution strategy with covariance matrix adaptation (CMA‐ES) does solve the given design optimization problem with high success rates and a large central barrier seems to be a superior feature.
Abstract: [1] Funnel-and-gate systems (FGSs), which constitute a common variant of permeable reactive barriers used for in situ treatment of groundwater, pose particular challenges to the task of design optimization. Because of the complex interplay of funnels and gates, the evolutionary algorithms applied have to cope with multimodality, nonseparability, and nonlinearity of the optimization task. We analyze these features in a test case, introducing an objective function for design cost and constraints to account for plume capture and detention time in the gate reactors. We show that the derandomized evolution strategy with covariance matrix adaptation (CMA-ES) does solve the given design optimization problem with high success rates. We further examine the performance of the algorithm for the example of four-gate systems in three heterogeneous template aquifers. Here a special focus is set on the parameterization of the FGS (i.e., the problem encoding). The comparison of three different encodings reveals their significance concerning the search progress and its success. Among the found optimal and near-optimal design solutions, mutual patterns were recognized. In particular, a large central barrier seems to be a superior feature.

Journal ArticleDOI
TL;DR: In this paper, a dual-channel-output all-optical logic AND gate was proposed and demonstrated using cascaded sum-and difference-frequency generation in a periodically poled lithium niobate (PPLN) waveguide.
Abstract: Proposed and demonstrated is a novel scheme of a dual-channel-output all-optical logic AND gate. Using cascaded sum- and difference-frequency generation in a periodically poled lithium niobate (PPLN) waveguide, 20 Gbit/s logic AND operation with dual-channel outputs is successfully observed in the experiment.

Patent
25 Oct 2007
TL;DR: In this paper, a flat panel display includes pixel electrodes, multiplexers and a gate driver with an amorphous silicon gate structure and includes a displacement temporary storage unit having a plurality of shift registers each with a power supply source and a clock terminal.
Abstract: A flat panel display includes pixel electrodes, multiplexers and a gate driver. The gate driver has an amorphous silicon gate structure and includes a displacement temporary storage unit having a plurality of shift registers each with a power supply source and a clock terminal. One of a first voltage and a second voltage is selected and transmitted to the power supply source, and one of the first voltage and a clock signal is selected and transmitted to the clock terminal according to an off-controlling signal for causing the pixel electrodes connected to the shift registers to discharge.

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A"V"O) and cut-off frequency (f"T) in nanoscale double gate (DG) devices.

Patent
19 Dec 2007
TL;DR: In this paper, an interlayer-dielectric film is used to avoid the need for gap fill requirements presented by adjacent gates by forming a trench in the interlayer dielectric layer, followed by the deposition of the gate material in the trench.
Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Patent
19 Apr 2007
TL;DR: In this article, a hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap, incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps.
Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density.

Journal ArticleDOI
TL;DR: In this paper, the transport properties of Si-nanowire (SiNW) field effect transistors have been investigated in a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework.
Abstract: We report atomistic simulations of the transport properties of Si-nanowire (SiNW) field-effect transistors. Results have been obtained within a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework. We analyze in detail the operation of an ultrascaled SiNW channel device and study the characteristics and transfer characteristics behavior of the device while varying several parameters including doping, gate and oxide lengths, and temperature. We focus our attention to the quantum capacitance of the SiNW and show that a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the principle of operation of this transfer scheme by implementing it in a nuclear magnetic resonance quantum-information processor, and demonstrate that the fidelity of the transfer can asymptotically approach unity.
Abstract: Transferring quantum information between two qubits is a basic requirement for many applications in quantum communication and quantum-information processing. In the iterative quantum-state transfer proposed by Burgarth et al. [Phys. Rev. A 75, 062327 (2007)], this is achieved by a static spin chain and a sequence of gate operations applied only to the receiving end of the chain. The only requirement on the spin chain is that it transfers a finite part of the input amplitude to the end of the chain, where the gate operations accumulate the information. For an appropriate sequence of evolutions and gate operations, the fidelity of the transfer can asymptotically approach unity. We demonstrate the principle of operation of this transfer scheme by implementing it in a nuclear magnetic resonance quantum-information processor.

Patent
29 Aug 2007
TL;DR: In this paper, a display device and a driving method are provided to block movement of dopants in a display panel by forming the same direction field between pixels which are connected to the same data drivers.
Abstract: A display device and a driving method thereof are provided to block movement of dopants in a display panel by forming the same direction field between pixels which are connected to the same data drivers. A display device includes a display panel(150), and gate and data drivers(140,120). The display panel includes plural gate lines in a first direction, plural data lines formed in a second direction crossing the first direction, and plural pixels formed on regions defined by the gate and data lines. The gate and data drivers apply scan and image signals to the gate and data lines, respectively, in response to control signals from outside. The data driver divides predetermined pixels, which are adjacent in at least one of the first and second directions, into plural groups, alternately supplies positive and negative image signals to the pixels every frame, and supplies image signals with different polarities to the adjacent groups.

Patent
25 Jan 2007
TL;DR: In this paper, a programming method for phase-change random access memory (PRAM) is presented. But the method is not suitable for the use of a single-input single-output (SISO) memory.
Abstract: A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.

Patent
02 Nov 2007
TL;DR: An IC solution utilizing mixed FPGA and MLC arrays is proposed in this article, where the process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier SBD, and multi-level cell (MLC) flash transistors.
Abstract: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions.