Showing papers on "AND gate published in 2009"

All-optical ultracompact photonic crystal AND gate based on nonlinear ring resonators

Abstract: We have proposed an ultracompact all-optical photonic crystal AND gate based on nonlinear ring resonators, consisting of two Kerr nonlinear photonic crystal ring resonators inserted between three parallel line defects. We have employed a Si nanocrystal as the nonlinear material for its appropriate nonlinear properties. The gate has been simulated and analyzed by finite difference time domain and plane wave expansion methods. The proposed logic gate can operate with a bit rate of about 120 Gbits/s.

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

Abstract: A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices. The drive currents at I off =100 nA/µm with V DD =1 V is 1.4 mA/µm and 0.6 mA/µm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V T of 0.3/-0.4V, good V T -uniformity, and V T -matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

$1/f$ Noise in Drain and Gate Current of MOSFETs With High- $k$ Gate Stacks

Abstract: In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.

Network analysis of biochemical logic for noise reduction and stability: a system of three coupled enzymatic and gates.

Abstract: We develop an approach aimed at optimizing the parameters of a network of biochemical logic gates for reduction of the "analog" noise buildup. Experiments for three coupled enzymatic AND gates are reported, illustrating our procedure. Specifically, starch, one of the controlled network inputs, is converted to maltose by beta-amylase. With the use of phosphate (another controlled input), maltose phosphorylase then produces glucose. Finally, nicotinamide adenine dinucleotide (NAD(+)), the third controlled input, is reduced under the action of glucose dehydrogenase to yield the optically detected signal. Network functioning is analyzed by varying selective inputs and fitting standardized few-parameters "response-surface" functions assumed for each gate. This allows a certain probe of the individual gate quality, but primarily yields information on the relative contribution of the gates to noise amplification. The derived information is then used to modify our experimental system to put it in a regime of a less noisy operation.

Digital analysis of protein properties by an ensemble of DNA quadruplexes.

Abstract: Here we show how different principles developed in the area of molecular logic gates can be applied to diagnostic technologies for proteins. Simultaneous operation of YES NOT and PASS 1 logic gates, produced by a protein sensing ensemble of DNA G-quadruplexes, is used to encode concentration levels of medicinally important proteins. An AND logic gate is another example, where molecular computation can be used to follow the interaction between proteins and metal ions. Combination of molecular Boolean logic with combinatorial sensing is demonstrated as a general strategy to realizing small scale, real time diagnosis of a variety of protein samples.

Synthesis of Fault Tolerant Reversible Logic Circuits

Abstract: Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

Abstract: An automated method and apparatus for positioning gate array circuits in an integrated circuit design An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits

Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders

Abstract: Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

Analysis of NMOS and PMOS Difference in $V_{T}$ Variation With Large-Scale DMA-TEG

Abstract: The mechanism of the VT variation difference between NMOS and PMOS is investigated. It is clarified that there is no correlation between VT and physical parameters such as gate length, gate width, gate oxide thickness, gate taper angle, sidewall width, channel strain, and gate poly-Si grain structure by integrated physical analysis (IPA). In IPA, the physical parameters of transistors with VT of -5sigma, median, and +5sigma are evaluated. It is also clarified that the variations of gate depletion and random charges at the gate oxide interface are not the dominant factors of VT variation, by electrical analyses using the Takeuchi plot. In these analyses, VT variations with varying process parameters are investigated. As a result of the analyses, only random channel dopant fluctuation (RDF) has a significant effect on VT variation. Since the simple RDF model alone cannot explain the VT variation difference between NMOS and PMOS, the channel boron clustering model is proposed as a possible mechanism of NMOS VT enhancement.

Dopant distribution in gate electrode of n- and p-type metal-oxide-semiconductor field effect transistor by laser-assisted atom probe

Abstract: Three dimensional dopant distributions in polycrystalline Si gate of n-type (n-) and p-type (p-) metal-oxide-semiconductor field effect transistor (MOSFET) structure were investigated by laser-assisted three dimensional atom probe. The remarkable difference in dopant distribution between n-MOSFET and p-MOSFET was clearly observed. In n-MOSFET gate, As and P atoms were segregated at grain boundaries and the interface between gate and gate oxide. No diffusion of As and P atoms into the gate oxide was observed. On the other hand, in p-MOSFET, no segregations of B atoms at grain boundaries or the interface were observed, and diffusion of B atoms into the gate oxide was directly observed.

Analog Noise Reduction in Enzymatic Logic Gates

Abstract: In this work, we demonstrate both experimentally and theoretically that the analog noise generation by a single enzymatic logic gate can be dramatically reduced to yield gate operation with virtually no input noise amplification. We demonstrate that when a cosubstrate with a much smaller affinity than the primary substrate is used, a negligible increase in the noise output from the logic gate is obtained, as compared to the input noise level. Our general theoretical conclusions were confirmed by experimental realizations of the AND logic gate based on the enzyme horseradish peroxidase using hydrogen peroxide as the substrate, with 2,2'-azino-bis(3-ethylbenzthiazoline-6-sulfonic acid) or ferrocyanide as cosubstrates with vastly different rate constants.

High-Voltage Auxiliary Power Supply Using Series-Connected MOSFETs and Floating Self-Driving Technique

Abstract: This paper deals with high-voltage auxiliary switching-mode power supplies (SMPSs) An overview of the state of the art is given, and a novel solution is proposed The proposed solution is based on a single-ended flyback or forward topology with the main switch arranged as a series connection of two metal-oxide-semiconductor field-effect transistors (MOSFETs) The bottom MOSFET is driven directly by an ordinary control circuit and gate driver, while the top MOSFET is driven by a floating self-supplied gate driver The floating gate driver is connected to the input filter capacitors' midpoint This gate driver plays two roles: driving of the top MOSFET and control of distribution of the blocking voltage among the series-connected MOSFETs, in steady state as well as during commutation The series connection of lower voltage MOSFETs has two important advantages compared to that of a single high-voltage MOSFET: lower conduction losses and lower cost When several switches are series connected, each switch supports a fraction of the total blocking voltage, and therefore, each switch can be rated for lower voltage The total on-state resistance and the cost of such a switch arrangement are lower compared to that of a single switch that supports the full blocking voltage The proposed SMPS is theoretically analyzed and experimentally verified The experimental results are presented and discussed

Modeling Gate Congestion of Marine Container Terminals, Truck Waiting Cost, and Optimization:

Abstract: As a consequence of the continuing growth of container volume and the introduction of 13,000 containerships carrying 20-ft-equivalent-unit (TEU) containers into major trade routes, the port industry is under pressure to come up with the necessary capacity to accommodate the increasing freight volume. One critical issue is the gate capacity of marine container terminals. Limited gate capacity leads to congestion. The harbor trucking industry operates in a competitive environment, and gate congestion is detrimental to its economic well-being. This paper applies a multiserver queuing model to analyze gate congestion and to quantify the truck waiting cost. An optimization model was developed to minimize the total gate system cost with data from field observations. A case study was applied to analyze gate congestion behavior and the truck waiting cost. The sensitivity of the model is discussed. With optimization, the truck waiting cost can be drastically reduced. Several congestion mitigation alternatives can ...

Inverter, method of operating the same and logic circuit comprising inverter

Abstract: Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor (T1) and a driving transistor (T2), and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.

Method of fabricating finfet device

Abstract: The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions.

Shift register and gate driver therefor

Abstract: The present invention relates to a shift register and a gate driver therefor. The shift register comprises: a first thin film transistor, of which a gate is connected to a first node, a source is connected to a clock signal terminal, and a drain is connected to an output terminal at current stage; a second thin film transistor, of which a gate is connected to a second node, a source is connected to the output terminal at current stage, and a drain is connected to a low level signal terminal; a third thin film transistor, of which a gate is connected to the first node, a source is connected to the low level signal terminal, and a drain is connected to the second node; a fourth thin film transistor, of which a gate is connected to the second node, a source is connected to the low level signal terminal, and a drain is connected to the first node; a first capacitor connected between the clock signal terminal and the second node; a discharging module connected between the clock signal terminal and the output terminal at current stage; a compensation module connected between the first node and the low level signal terminal. The present invention has the advantages of low cost, low power consumption and long life span etc, as well as the features of high stability, strong anti-interference capability and small delay etc.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Abstract: In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

A fluorescent AND logic gate driven by electrons and protons

Abstract: A molecular logic gate displays a fluorescence output after oxidation in acidic media according to AND logic.

Multirate, Differentiated-QoS, and Multilevel Fiber-Optic CDMA System via Optical Logic Gate Elements

Abstract: In this paper, we present a novel multirate, differentiated quality of service (QoS) optical CDMA (OCDMA) system using multilevel signaling technique. The emphasis is on OCDMA systems employing multi-length variable-weight optical orthogonal codes (MLVW-OOC) as signature sequence. We begin by presenting a two-class variable-weight OCDMA system in which all users have the same energy level in one bit duration. As a consequence, high weight users transmit their corresponding optical pulses at a lower power while low weight users transmit their corresponding optical pulses at a higher power level. We show that using this multilevel signaling technique, while employing the well known optical AND logic gate receiver structure, we achieve a considerable improvement in the performance of low-weight (high-power) users while the performance of high-weight (low-power) users not altered in comparison to one-level system. In the next step, we indicate that by using the recently introduced multistage receiver structure, which employs advanced optical logic gate elements, interferences at different power levels are distinguishable so that the performance of both high-weight and low-weight users are improved. Furthermore, we employ multilevel signaling technique in OCDMA system based on MLVW-OOC (multirate, differentiated QoS system). We show that using multilevel signaling technique in such a system results to the performance improvement. To analyze the performance of the system we obtain a closed-form relation expressing an upper bound on the probability of error of the system. Finally, to validate the upper bound, the analytical results are compared to the results of system simulation. The numerical closeness between the analytical and system simulation reveals the tightness of the obtained upper bound, hence making them quite useful in evaluating the above system's performance.

Scalable don't-care-based logic optimization and resynthesis

Abstract: We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes.

Analog Noise Reduction in Enzymatic Logic Gates

Abstract: In this work we demonstrate both experimentally and theoretically that the analog noise generation by a single enzymatic logic gate can be dramatically reduced to yield gate operation with virtually no input noise amplification. This is achieved by exploiting the enzyme's specificity when using a co-substrate that has a much lower affinity than the primary substrate. Under these conditions, we obtain a negligible increase in the noise output from the logic gate as compared to the input noise level. Experimental realizations of the AND logic gate with the enzyme horseradish peroxidase using hydrogen peroxide and two different co-substrates, 2,2'-azino-bis(3-ethylbenzthiazoline-6-sulphonic acid) (ABTS) and ferrocyanide, with vastly different rate constants confirmed our general theoretical conclusions.

High-reliability gate driving circuit

Abstract: A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.

Method of driving a gate line and gate drive circuit for performing the method

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Simultaneous low-frequency noise characterization of gate and drain currents in AlGaN/GaN high electron mobility transistors

Abstract: Room temperature low frequency noise characteristics of gate and drain currents of an AlGaN/GaN high electron mobility transistor are reported. A Hooge parameter (αH) ranging from 10−3 to 10−4 is extracted for drain current noise as a function of sheet carrier density. Gate current noise is simultaneously measured with drain noise both in the time and frequency domain. A weak correlation is seen between the drain and gate noise. Temporally unstable Lorentzian components on top of stable 1/fγ noise are observed in the gate noise spectra which also show up as random telegraph signal noise in the time domain. It is proposed that the gate Schottky contact is of high quality but that electrically unstable point defects in the AlGaN layer are the cause of Lorentzians and random telegraph switching noise.