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Showing papers on "AND gate published in 2011"


Journal ArticleDOI
TL;DR: An orthogonal AND gate in Escherichia coli is constructed using a novel hetero-regulation module from Pseudomonas syringae and demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate.
Abstract: Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts.

370 citations


Journal ArticleDOI
TL;DR: A molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder,half-subtractor, multiplexer, demultiplexers, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state are reported.
Abstract: Photochromes are photoswitchable, bistable chromophores which, like transistors, can implement binary logic operations. When several photochromes are combined in one molecule, interactions between them such as energy and electron transfer allow design of simple Boolean logic gates and more complex logic devices with all-photonic inputs and outputs. Selective isomerization of individual photochromes can be achieved using light of different wavelengths, and logic outputs can employ absorption and emission properties at different wavelengths, thus allowing a single molecular species to perform several different functions, even simultaneously. Here, we report a molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder, half-subtractor, multiplexer, demultiplexer, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state. The system demonstrates the advantages of light-responsive molecules as multifunctional, reconfigurable nanoscale logic devices that represent an approach to true molecular information processing units.

275 citations


Book
15 Apr 2011
TL;DR: This book contains a highly accessible introduction to GATE Version 6 and is the first port of call for all GATE-related questions, and includes a guide to using GATE Developer and GATE Embedded, and chapters on all major areas of functionality, such as processing multiple languages and large collections of unstructured text.
Abstract: GATE is a free open-source infrastructure for developing and deploying software components that process human language. It is more than 15 years old and is in active use for all types of computational tasks involving language (frequently called natural language processing, text analytics, or text mining). GATE excels at text analysis of all shapes and sizes. From large corporations to small startups, from multi-million research consortia to undergraduate projects, our user community is the largest and most diverse of any system of this type, and is active world-wide. This book contains a highly accessible introduction to GATE Version 6 and is the first port of call for all GATE-related questions. It includes a guide to using GATE Developer and GATE Embedded, and chapters on all major areas of functionality, such as processing multiple languages and large collections of unstructured text. It also includes complete plugin documentation (e.g. named entity recognition, parsing, semantic analysis, , as well as details on other members of the GATE Family: GATECloud.net, Teamware, and Mimir. To join the GATE community visit http://gate.ac.uk/.

262 citations


Journal ArticleDOI
TL;DR: In this paper, reversible logic circuits made of DNA have been proposed, based on an AND gate that is designed to be thermodynamically and kinetically reversible and to respond nonlinearly to the concentrations of its input molecules.
Abstract: We report reversible logic circuits made of DNA. The circuits are based on an AND gate that is designed to be thermodynamically and kinetically reversible and to respond nonlinearly to the concentrations of its input molecules. The circuits continuously recompute their outputs, allowing them to respond to changing inputs. They are robust to imperfections in their inputs.

159 citations


Journal ArticleDOI
TL;DR: A bacteria-based AND logic gate using a Pseudomonas aeruginosa lasI/rhlI double mutant with two quorum-sensing signaling molecules as the input signals showed a distinct electrical output signal, despite the complexity and continuous regulation of metabolic reactions of living cells.

129 citations


Journal ArticleDOI
TL;DR: In this paper, thin-body tunneling field effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics are investigated.
Abstract: We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

112 citations


Journal ArticleDOI
TL;DR: Using the stochastic Landau-Lifshitz-Gilbert equation, it is shown that the amount of energy dissipated during nanomagnet erasure approaches Landauer's thermodynamic limit of kTln(2) with high precision when the external magnetic fields are applied slowly.
Abstract: Nanomagnetic memory and logic circuits are attractive integrated platforms for studying the fundamental thermodynamic limits of computation. Using the stochastic Landau-Lifshitz-Gilbert equation, we show by direct calculation that the amount of energy dissipated during nanomagnet erasure approaches Landauer's thermodynamic limit of $kT\mathrm{ln} (2)$ with high precision when the external magnetic fields are applied slowly. In addition, we find that nanomagnet systems behave according to generalized formulations of Landauer's principle that hold for small systems and generic logic operations. In all cases, the results are independent of the anisotropy energy of the nanomagnet. Lastly, we apply our computational approach to a nanomagnet majority logic gate, where we find that dissipationless, reversible computation can be achieved when the magnetic fields are applied in the appropriate order.

103 citations


Journal ArticleDOI
TL;DR: Proposed logic gates have the potential to be key components for an optical packet switching system due to their small feature sizes and low power consumption.

100 citations


Proceedings ArticleDOI
08 Jun 2011
TL;DR: This paper develops a Functionality Enhanced All Spin Logic (FEASL) architecture and a synthesis framework using Logically Passively Self Dual (LPSD) formulation and synthesized Discrete Cosine Transform (DCT) algorithm using adders and multipliers to show the efficacy of the proposed FEASL approach in designing digital signal processing (DSP) systems.
Abstract: Power consumption in CMOS integrated circuits increases every technology generation due to increased subthreshold and gate leakage currents. To cope with such a problem, researchers have started looking at the possibility of logic devices based on electron spin, as an alternative to charge based CMOS, for realizing low-power integrated circuits with low active power dissipation and zero standby leakage. In this paper, we investigate spin-based logic devices that employ low-power spin-torque switching mechanism for circuit operation. We have developed a Functionality Enhanced All Spin Logic (FEASL) architecture and a synthesis framework using Logically Passively Self Dual (LPSD) formulation. This methodology enables the design of large functional logic blocks, especially low-power adders and multipliers, which constitute the building blocks of all arithmetic logic units (ALU). In addition, we have investigated three different variants of ASL, which are low-power, medium-power -- medium performance and high performance and we analyze their merits and drawbacks at circuit/architecture level. We synthesized Discrete Cosine Transform (DCT) algorithm using adders and multipliers to show the efficacy of the proposed FEASL approach in designing digital signal processing (DSP) systems. Compared to 15nm CMOS implementation, the FEASL based DCT shows 88% improvement in power and 83% in PDP with 43% degradation in performance.

86 citations


Journal ArticleDOI
Yun Ye1, Frank Liu2, Min Chen1, Sani R. Nassif2, Yu Cao1 
TL;DR: An efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process is developed.
Abstract: The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process. By understanding the physical principles of atomistic simulations, we: 1) identify the appropriate method to divide a nonuniform gate into slices in order to map those fluctuations into the device model; 2) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth ; 3) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations; and 4) investigate the interaction with non-rectangular gate (NRG) and reverse narrow width effect (RNWE). The proposed SPICE simulation method is validated with atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.

84 citations


Journal ArticleDOI
TL;DR: In this article, a reliability block diagram with general gates (RBDGG) was developed as an intuitive and easy-to-use method for system reliability analysis, which allows node connection relations of general gates such as the AND gate and the k-out-of-n gate other than the OR gate connection relation.

Proceedings ArticleDOI
06 Mar 2011
TL;DR: The presented topology, which consists of a class E inverter, class E rectifier, and self-oscillating gate driver, is inherently resonant, and switching losses are greatly reduced by ensuring Zero Voltage Switching of the power semiconductor devices.
Abstract: This paper describes the analysis and design of a DC-DC converter topology which is operational at frequencies in the Very High Frequency (VHF) band ranging from 30 MHz–300 MHz. The presented topology, which consists of a class E inverter, class E rectifier, and self-oscillating gate driver, is inherently resonant, and switching losses are greatly reduced by ensuring Zero Voltage Switching (ZVS) of the power semiconductor devices. A design method to ensure ZVS operation when combining the inverter, rectifier, and gate driver is provided. Several parasitic effects and their influence on converter operation are discussed, and measurement results of a 100 MHz prototype converter are presented and evaluated. The designed prototype converter verifies the described topology.

Proceedings Article
14 Jun 2011
TL;DR: In this paper, gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence.
Abstract: We report on gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ∼5A is demonstrated in gate-last, with high-k deposited first, through the use of an Etch-Stop-Layer with composite nature and similar TDDB reliability to gate-first; 2) controlled alloying for EWF engineering is obtained by careful material selection and tuned metals thicknesses ratio; 3) suppression of abnormal L gate - and W gate -dependence on J G , EOT and NBTI for devices with both high-k and metal deposited last (L gate ≥35nm, W gate ≥80nm) demonstrates the potential for improved UT-EOT control down to small devices with this scheme.

Journal ArticleDOI
TL;DR: AlGaN/GaN High Electron Mobility Transistors with various gate lengths have been step-stressed under both on- and off-state conditions reveal that the Schottky contact is the source of degradation, and the electric field is the main mechanism for degradation.

Journal ArticleDOI
TL;DR: In this article, capacitive field-effect sensors based on a p-Si-SiO2-Ta2O5 structure modified with a multi-enzyme membrane have been used for electronic transduction of biochemical signals processed by enzyme-based OR and AND logic gates.

Patent
04 Feb 2011
TL;DR: In this article, a power converter with an arm including switching devices connected in parallel, realizing long lifespans of switching devices, is presented, where an inverter includes an upper and a lower arm, and gate drive circuits each driving the corresponding arm according to a gate control signal Gup_s indicating ON/OFF periods.
Abstract: The present invention aims to provide a power converter with an arm including switching devices connected in parallel, realizing long lifespans of switching devices. An inverter includes an upper and a lower arm, and gate drive circuits each driving the corresponding arm according to a gate control signal Gup_s indicating ON/OFF periods. Each arm includes switching devices connected in parallel. Each gate drive circuit includes: a switching gate control circuit 230 u bringing a switching device 210 u into conduction at the beginning of the ON period and bringing the same out of conduction within the ON period; and a conduction gate control circuit 231 u bringing switching devices 211 u and 212 u within a period from when the switching device 210 u is brought into conduction until the same is brought out of conduction, wherein the switching device 210 u has a lower parasitic capacitance than the switching devices 211 u and the 212 u.

Patent
23 Jun 2011
TL;DR: In this article, a transistor device with carbon nanotube channels is described, which includes a substrate, an insulator on the substrate, a local bottom gate embedded in the insulator, a carbon-based nanostructure material over at least a portion of the local gate dielectric, and conductive source and drain contacts.
Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology.
Abstract: For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.

Journal ArticleDOI
TL;DR: In this paper, drain, transfer, and gate current characteristics are compared between two structures, showing a measurable difference in threshold voltage and transconductance, which suggests that at this stage in ALD development, Ta2O5 appears better suited for gate insulation of AlN/GaN HEMTs.
Abstract: AlN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (HEMTs) have been grown and fabricated which utilize a 6 nm thick atomic layer deposited film of either Ta2O5 or HfO2 for gate insulation. Drain, transfer, and gate current characteristics are compared between both structures, showing a measurable difference in threshold voltage and transconductance. The cause is highlighted by the results of capacitance-voltage analysis which showed 10 MHz dielectric constants of 8.7 and 11.7 for the HfO2 and Ta2O5 films, respectively. Furthermore, interface trap state density was extracted by Terman's method and compared between films. HEMT small signal frequency performance was representative of the different sub-micron gate lengths. Consideration of the compared electrical results suggests that at this stage in ALD development, Ta2O5 appears better suited for gate insulation of AlN/GaN HEMTs. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Journal ArticleDOI
TL;DR: In this paper, a flash-based FPGA was exposed to radiation to measure variations in current, temperature, propagation-delay and duty-cycle in logic circuits, and electrical simulations were carried out to study the difference of behavior in the degradation of different logic mappings.
Abstract: We exposed a flash-based FPGA to radiation to measure variations in current, temperature, propagation-delay and duty-cycle in logic circuits. Propagation-delay degradations vary from 400% to 1100% before functional failure, according to circuit and logical mapping. Electrical simulations are carried out to study the difference of behavior in the degradation of different logic mappings.

Journal ArticleDOI
TL;DR: In this paper, the thermal budget of gate-last and gate-first process for deep-submicron self-aligned InGaAs MOSFETs was investigated, and the authors concluded that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate first process.
Abstract: Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III–V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III–V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGa...

Journal ArticleDOI
TL;DR: It is demonstrated how device subthreshold leakage current and subth threshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering.

Journal ArticleDOI
30 Sep 2011
TL;DR: Rakhinarang et al. as mentioned in this paper proposed a Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, India rakinarang@gmail.com, mridula@south.du.co.in
Abstract: 1 Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, India rakhinarang@gmail.com, mridula@south.du.ac.in 2 Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India saxena_manoj77@yahoo.co.in 3 Department of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, Sector-22, Rohini, Delhi, India rsgu@bol.net.in

Patent
07 Mar 2011
TL;DR: In this paper, the authors proposed a gate drive circuit for applying a control signal from a control circuit to a gate of a switching element Q1 having a drain, source and gate and comprising a wide bandgap semiconductor to drive on/off the switching element.
Abstract: PROBLEM TO BE SOLVED: To provide a gate drive circuit that stably turns on a switching element without varying a turn-on switching characteristic nor causing a power loss.SOLUTION: The gate drive circuit for applying a control signal from a control circuit to a gate of a switching element Q1 having a drain, source and gate and comprising a wide bandgap semiconductor to drive on/off the switching element comprises: a parallel circuit of a first capacitor C1 and a first resistance R1 connected between the control circuit and the gate of the switching element; and short circuit means S4 connected between the gate and source of the switching element to short-circuit the gate and source with a delay from an off signal of the control signal.

Journal ArticleDOI
TL;DR: A new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented, complementary to application-independent detection methods for FPGAs.
Abstract: High resolution diagnosis plays a critical role in silicon debug and yield improvement. Application-dependent diagnosis is also a key component in online testing and adaptive computing. In this paper, a new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented. This work is complementary to application-independent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration with less than 5% overhead of built-in self diagnosis. These techniques have been further extended for multiple fault diagnosis.

Journal ArticleDOI
TL;DR: In this article, the impact of gate-stress position on the current collapse behavior of AlGaN/GaN high-electron-mobility transistors (HEMTs) without surface passivation was investigated.
Abstract: Using a dual-gate structure, we have investigated the impact of gate-stress position on the current collapse behavior of AlGaN/GaN high-electron-mobility transistors (HEMTs) without surface passivation. When the gate-bias stress under the off state was applied to the additional gate between the main gate and the drain electrode, we observed a marked increase in on-resistance (RON). On the other hand, the off-state stress on the main gate itself caused a decrease in drain saturation current as well as an increase in RON. The calculation of electric field at the AlGaN surface showed that the field peaks existed at the gate edges on both the drain and source sides, probably causing electron charging at the AlGaN surface near both gate-edge areas. These results indicated that the off-state gate stress induces "virtual gates" in the gate edges expanding in both the drain and source directions. The impacts of device structures on the current collapse have been characterized, using Schottky-gate HEMTs with and without surface passivation and metal–oxide–semiconductor (MOS) gate HEMTs. The surface passivation and MOS-gate structure was effective in mitigating current collapse, which was explained in terms of surface state density, electric field strength, and gate leakage current.

Patent
08 Nov 2011
TL;DR: In this paper, a control capacitor is connected between a pixel electrode of a liquid crystal capacitor (CLC_Bn) in at least one sub-pixel and a common signal line (COM) through a TFT (3 ) whose gate electrode is connected to a gate signal line.
Abstract: A control capacitor (CDown) is connected between a pixel electrode of a liquid crystal capacitor (CLC_Bn) in at least one sub-pixel and a common signal line (COM) through a TFT ( 3 ) whose gate electrode is connected to a gate signal line (Gn+1), and a control circuit selectively switches output modes in accordance with whether the pulse periods of a gate pulse to be output to the gate signal line (Gn) and a gate pulse to be output to the gate signal line (Gn+1) partially overlap or not.

Patent
06 May 2011
TL;DR: In this article, a common cut mask is employed to define a gate pattern and a local interconnect pattern, and the gate structure and local interconnection structures are formed with zero overlay variation relative to one another.
Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

Patent
22 Jun 2011
TL;DR: In this paper, an array substrate for a liquid crystal display device including a substrate having a display region and a non-display region at one side of the display region is presented.
Abstract: An array substrate for a liquid crystal display device including a substrate having a display region and a non-display region at one side of the display region; gate lines along a first direction and in the display region; data lines along a second direction and in the display region, the data lines crossing the gate lines to define pixel regions; auxiliary gate lines along the second direction and in the display region, the auxiliary gate lines respectively connected to the gate lines; data pad electrodes in the non-display region and electrically connected to the data lines, respectively; and gate pad electrodes in the non-display region and electrically connected to the auxiliary gate lines, respectively.

Patent
17 Feb 2011
TL;DR: In this article, a gate-all-around field effect transistor (GOFET) is constructed by forming a suspended fin in a semiconductor substrate, forming a gate stack around the fin, and forming source/drain regions in the fin on both sides of the gate stack.
Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.