Showing papers on "AND gate published in 2012"

Integrated Circuits Based on Bilayer MoS2 Transistors

Abstract: Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene’s advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic...

Genetic programs constructed from layered logic gates in single cells

Abstract: The creation of orthogonal ‘AND’ logic gates by combining DNA-binding proteins into complex, layered circuits opens the way to the design of programmable integrated circuits in synthetic biology. Synthetic genetic circuits tend to interfere with one another, a complication that restricts the number of circuits that can be used to program a cell. Chris Voigt and colleagues have mined a collection of DNA-binding proteins that depend on specific 'chaperone' proteins to activate the transcription of their target genes, and combined them into complex, layered circuits of orthogonal 'AND' logic gates. Using this system, the authors constructed one of the largest genetic programs built so far, consisting of seven integrated sensors/circuits and eleven regulatory proteins. This work opens the way for the design of programmable integrated circuits in synthetic biology. Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2,3,4,5,6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells.

Characterizing Quantum Gates via Randomized Benchmarking

Abstract: We describe and expand upon the scalable randomized benchmarking protocol proposed in Phys. Rev. Lett. 106, 180504 (2011) which provides a method for benchmarking quantum gates and estimating the gate dependence of the noise. The protocol allows the noise to have weak time and gate dependence, and we provide a sufficient condition for the applicability of the protocol in terms of the average variation of the noise. We discuss how state-preparation and measurement errors are taken into account and provide a complete proof of the scalability of the protocol. We establish a connection in special cases between the error rate provided by this protocol and the error strength measured using the diamond norm distance.

Integrated Circuits Based on Bilayer MoS

Abstract: Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene’s advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multi-stage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between two to twelve transistors seamlessly integrated side-byside on a single sheet of bilayer MoS2. Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions.

Symmetric multilevel inverter with reduced components based on non-insulated dc voltage sources

Abstract: Multilevel inverters have an important portion in power processing in power systems. These inverters have some inherent advantages such as ability to operate with high power and voltage, improved output waveform quality and flexibility which make them attractive and more popular. This study proposes a new topology based on the non-insulated dc voltage sources for multilevel inverter with reduced number of switching devices. As a result, it reduces control complexity and gate driver circuits. The proposed topology is a general topology which can be easily extended to a desired number of voltage levels. All of the desired output voltage levels (both odd and even) can be achieved using the proposed topology. The validity of the proposed multilevel inverter is verified with both computer simulation and experimental results from a 15-level laboratory prototype.

A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders

Abstract: Quantum dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the nanoscale. The basic Boolean primitive in QCA is the majority gate. In this paper we present a novel design for QCA cells and another possible and unconventional scheme for majority gates. By applying these items, the hardware requirements for a QCA design can be reduced and circuits can be simpler in level and gate counts. As an example, a 1-bit QCA adder is constructed by applying our new scheme and is compared to the other existing implementation. Beside, some Boolean functions are expressed as examples and it has been shown, how our reduction method by using new proposed item, decreases gate counts and levels in comparison to the other previous methods.

Genetic Circuit Performance under Conditions Relevant for Industrial Bioreactors

Abstract: Synthetic genetic programs promise to enable novel applications in industrial processes. For such applications, the genetic circuits that compose programs will require fidelity in varying and complex environments. In this work, we report the performance of two synthetic circuits in Escherichia coli under industrially relevant conditions, including the selection of media, strain, and growth rate. We test and compare two transcriptional circuits: an AND and a NOR gate. In E. coli DH10B, the AND gate is inactive in minimal media; activity can be rescued by supplementing the media and transferring the gate into the industrial strain E. coli DS68637 where normal function is observed in minimal media. In contrast, the NOR gate is robust to media composition and functions similarly in both strains. The AND gate is evaluated at three stages of early scale-up: 100 mL shake flask experiments, a 1 mL MTP microreactor, and a 10 L bioreactor. A reference plasmid that constitutively produces a GFP reporter is used to m...

Functional and logic programming

Abstract: proceedings of the 11th International symposium on Functional and Logic Programming (FLOPS 2012), held in Kobe, Japan, May 23-25, 2012

DNA computation: a photochemically controlled AND gate.

Abstract: DNA computation is an emerging field that enables the assembly of complex circuits based on defined DNA logic gates. DNA-based logic gates have previously been operated through purely chemical means, controlling logic operations through DNA strands or other biomolecules. Although gates can operate through this manner, it limits temporal and spatial control of DNA-based logic operations. A photochemically controlled AND gate was developed through the incorporation of caged thymidine nucleotides into a DNA-based logic gate. By using light as the logic inputs, both spatial control and temporal control were achieved. In addition, design rules for light-regulated DNA logic gates were derived. A step-response, which can be found in a controller, was demonstrated. Photochemical inputs close the gap between DNA computation and silicon-based electrical circuitry, since light waves can be directly converted into electrical output signals and vice versa. This connection is important for the further development of an...

An Energy-Efficient Memristive Threshold Logic Circuit

Abstract: Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

Design and simulation of an all-optical photonic crystal AND gate using nonlinear Kerr effect

Abstract: A photonic crystal optical limiter with a sharp input-output characteristic curve is initially designed in this paper. Thereafter; using an optimized Y-junction, a new topology for an all-optical photonic crystal AND gate is proposed. The mentioned gate has a transition time less than 1 ps, a delay time less than 0.4 ps and occupies an area less than 100 μm2. The 1,550 nm input lasers should have a power equal to 10W to be able to trigger the switching mechanism. The photonic crystal used for this purpose is a two dimensional triangular lattice of holes in a GaAs substrate. PWE and FDTD methods are used to simulate the proposed structure. Time domain simulations confirm the switching mechanism of the proposed AND gate.

Shift register and gate driving circuit using the same

Abstract: Disclosed are a shift register, and a gate driving circuit including a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device. Each shift register includes: an input unit which outputs a directional input signal having a gate high or low voltage based on an output signal from a previous or subsequent shift register to a first node; an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; and an output unit which includes a pull-up unit connected to the first node and activating an output clock signal based on the signal at the first node, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node.

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

Abstract:  Abstract—In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960. Moreover, the power consumption can be reduced from 1.26mw to 0.37mw as well as power delay product reduced from 2.14mw*ns to 1.28mw*ns.

Magnetization dynamics, throughput and energy dissipation in a universal multiferroic nanomagnetic logic gate with fan-in and fan-out.

Abstract: The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau?Lifshitz?Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ?50?mV applied to the piezoelectric layer generating 10.1?MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ?0.5?GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2?ns with a latency of 4?ns. The total (internal?+?external) energy dissipated for a single gate operation at this throughput rate is found to be only ?500?kT in the gate and ?1250?kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively three and five orders of magnitude more energy-efficient than complementary-metal?oxide?semiconductor-transistor (CMOS)-based and spin-transfer-torque-driven nanomagnet-based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be three orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing.

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Abstract: In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

Control of efficiency, brightness, and recombination zone in light-emitting field effect transistors.

Abstract: The split-gate light emitting field effect transistors (SG-LEFETs) demonstrate a new strategy for ambipolar LEFETs to achieve high brightness and efficiency simultaneously. The SG architecture forces largest quantity of opposite charges on Gate 1 and Gate 2 area to meet in the center of the channel. By actively and independently controlling current injection from separated gate electrodes within transporting channel, high brightness can be obtained in the largest injection current regime with highest efficiency.

Majority Gate for Nanomagnetic Logic With Perpendicular Magnetic Anisotropy

Abstract: A majority gate for nanomagnetic logic with perpendicular magnetic anisotropy is presented. A novel technique of local focused ion beam irradiation generating artificial domain wall nucleation centers is used to enable directed signal flow and logic computation in an array of field-coupled nanomagnets. The switching behavior of the majority gate is characterized and logic operation is experimentally proven using magneto-optical and magnetic force microscopy. The findings are supported by numerical and micromagnetic simulations. Tolerance margins for fabrication and computing frequencies for correct operation are explored. The presented majority gate allows for complex, non-volatile logic with synchronous global clocking at room-temperature.

Realizing Lateral Wrap-Gated Nanowire FETs: Controlling Gate Length with Chemistry Rather than Lithography.

Abstract: An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the subthreshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 and 4 K, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.

Driving method for display device

Abstract: A liquid crystal display includes pixels each having an switching element, drain drivers and gate drivers for operating the switching elements and the pixels, and drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer. Wiring lines are formed on the one of a pair of substrates for transferring display data signals and a clock signal to the gate drivers.

Realizing lateral wrap-gated nanowire FETs: Controlling gate length with chemistry rather than lithography

Abstract: An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the sub-threshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 to 4 Kelvin, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.

Performance evaluation of SiC power MOSFETs for high-temperature applications

Abstract: In this paper, the high-temperature performance of the commercial SiC power MOSFETs has been extensively evaluated beyond 125 °C - the maximum junction temperature according to the datasheet. Both the static and switching characteristics have been measured under various temperatures up to 200 °C. The results show the superior electrical performance of the SiC MOSFETs for high-temperature operation. Meanwhile, the gate biasing and gate switching tests have also been conducted to test the gate oxide reliability of these devices under elevated temperatures. The test results reveal the degradation in the device characteristics under high temperature and different gate voltage conditions, which exhibit the trade-off between the performance and the reliability of SiC MOSFETs for high-temperature applications.

Explicit modeling of control and data for improved NoC router estimation

Abstract: Networks-on-Chip (NoCs) are scalable fabrics for interconnection networks used in many-core architectures. ORION2.0 is a widely adopted NoC power and area estimation tool; however, its models for area, power and gate count can have large errors (up to 110% on average) versus actual implementation. In this work, we propose a new methodology that analyzes netlists of NoC routers that have been placed and routed by commercial tools, and then performs explicit modeling of control and data paths followed by regression analysis to create highly accurate gate count, area and power models for NoCs. When compared with actual implementations, our new models have average estimation errors of no more than 9.8% across microarchitecture and implementation parameters. We further describe modeling extensions that enable more detailed flit-level power estimation when integrated with simulation tools such as GARNET.

Vertical nanowire transistor with axially engineered semiconductor and gate metallization

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length

On-Chip Clocking of Nanomagnet Logic Lines and Gates

Abstract: The nanomagnet logic (NML) devices considered here are variants of proposed components for the edge-driven, quantum-dot cellular automata device architecture, where the position of electrons on quantum dots was suggested as a mechanism for representing binary state. To control NML circuit components (e.g., gates and lines), to date, externally generated magnetic fields have served as a clock. The clock is used to make the magnets in a circuit ensemble transition to a metastable state, so fringing fields from individual devices can set the state of a neighboring device in accordance with a new input. However, such a clocking scheme is obviously not extensible to chip-level systems. For NML to be a viable candidate for digital systems, a mechanism for simultaneously modulating the energy barriers of a group of devices must be implemented “on-chip,” and guarantee unidirectional dataflow from circuit input to circuit output. We have experimentally demonstrated a CMOS-compatible clock, and used it to reevaluate all of the NML constructs required for a functionally complete logic set. All possible input combinations to said constructs were successfully considered. Experiments were designed to promote unidirectional dataflow.

Enzyme-based logic analysis of biomarkers at physiological concentrations: and gate with double-sigmoid "filter" response.

Abstract: We report the first realization of a biomolecular AND gate function with double-sigmoid response (sigmoid in both inputs). Two enzyme biomarker inputs activate the gate output signal, which can then be used as indicating liver injury, but only when both of these inputs have elevated pathophysiological concentrations, effectively corresponding to logic-1 of the binary gate functioning. At lower, normal physiological concentrations, defined as logic-0 inputs, the liver-injury output levels are not obtained. High-quality gate functioning in handling of various sources of noise, on time scales of relevance to potential applications, is enabled by utilizing “filtering” effected by a simple added biocatalytic process. The resulting gate response is sigmoid in both inputs when proper system parameters are chosen, and the gate properties are theoretically analyzed within a model devised to evaluate its noise-handling properties.

Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

Abstract: With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.