Showing papers on "AND gate published in 2019"

Performance Evaluation of High-Power SiC MOSFET Modules in Comparison to Si IGBT Modules

Abstract: The higher voltage blocking capability and faster switching speed of silicon-carbide (SiC) mosfet s have the potential to replace Si insulated gate bipolar transistors (IGBTs) in medium-/low-voltage and high-power applications. In this paper, a state-of-the-art commercially available 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability. Meanwhile, Si IGBT modules with similar power ratings are also tested under the same conditions. From the test results, several interesting points have been obtained: different to the Si IGBT module, the over-shoot current of the SiC mosfet module increases linearly with the increase of the load current and it has been explained by a model of the over-shoot current proposed in this paper; the induced negative gate voltage due to the complementary device turn- off (crosstalk effect) is more harmful to the SiC mosfet module than the induced positive gate voltage during turn- on when the gate off-voltage is –6 V; the maximum dv / dt and di / dt (electromagnetic interference) during switching transients of the SiC mosfet module are close to those of the Si IGBT module when the gate resistance is larger than 8 Ω but the switching loss of the SiC mosfet module is much smaller; the switching losses of the Si IGBT module are greater than those of the SiC mosfet module even when the gate resistance of the former is reduced to zero. An accurate power loss model, which is suitable for a three-phase two-level converter based on SiC mosfet modules considering the power loss of the parasitic capacitance, has been presented and verified in this paper. From the model, a 96.2% efficiency can be achieved at the switching frequency of 80 kHz and the power of 100 kW.

Neural Logic Machines

Abstract: We propose the Neural Logic Machine (NLM), a neural-symbolic architecture for both inductive learning and logic reasoning. NLMs exploit the power of both neural networks---as function approximators, and logic programming---as a symbolic processor for objects with properties, relations, logic connectives, and quantifiers. After being trained on small-scale tasks (such as sorting short arrays), NLMs can recover lifted rules, and generalize to large-scale tasks (such as sorting longer arrays). In our experiments, NLMs achieve perfect generalization in a number of tasks, from relational reasoning tasks on the family tree and general graphs, to decision making tasks including sorting arrays, finding shortest paths, and playing the blocks world. Most of these tasks are hard to accomplish for neural networks or inductive logic programming alone.

Variational Quantum State Diagonalization

Abstract: Variational hybrid quantum-classical algorithms are promising candidates for near-term implementation on quantum computers. In these algorithms, a quantum computer evaluates the cost of a gate sequence (with speedup over classical cost evaluation), and a classical computer uses this information to adjust the parameters of the gate sequence. Here we present such an algorithm for quantum state diagonalization. State diagonalization has applications in condensed matter physics (e.g., entanglement spectroscopy) as well as in machine learning (e.g., principal component analysis). For a quantum state ρ and gate sequence U, our cost function quantifies how far $$U\rho U^\dagger$$ is from being diagonal. We introduce short-depth quantum circuits to quantify our cost. Minimizing this cost returns a gate sequence that approximately diagonalizes ρ. One can then read out approximations of the largest eigenvalues, and the associated eigenvectors, of ρ. As a proof-of-principle, we implement our algorithm on Rigetti’s quantum computer to diagonalize one-qubit states and on a simulator to find the entanglement spectrum of the Heisenberg model ground state.

Gradients of parameterized quantum gates using the parameter-shift rule and gate decomposition

Abstract: The parameter-shift rule is an approach to measuring gradients of quantum circuits with respect to their parameters, which does not require ancilla qubits or controlled operations. Here, I discuss applying this approach to a wider range of parameterize quantum gates by decomposing gates into a product of standard gates, each of which is parameter-shift rule differentiable.

Machine learning method for state preparation and gate synthesis on photonic quantum computers

Abstract: We show how techniques from machine learning and optimization can be used to find circuits of photonic quantum computers that perform a desired transformation between input and output states. In the simplest case of a single input state, our method discovers circuits for preparing a desired quantum state. In the more general case of several input and output relations, our method obtains circuits that reproduce the action of a target unitary transformation. We use a continuous-variable quantum neural network as the circuit architecture. The network is composed of several layers of optical gates with variable parameters that are optimized by applying automatic differentiation using the TensorFlow backend of the Strawberry Fields photonic quantum computer simulator. We demonstrate the power and versatility of our methods by learning how to use short-depth circuits to synthesize single photons, Gottesman-Kitaev-Preskill states, NOON states, cubic phase gates, random unitaries, cross-Kerr interactions, as well as several other states and gates. We routinely obtain high fidelities above 99% using short-depth circuits, typically consisting of a few hundred gates. The circuits are obtained automatically by simply specifying the target state or gate and running the optimization algorithm.

The switching of optoelectronics to full optical computing operations based on nonlinear metamaterials

Abstract: The recent progress in optical computing outlines the fact that electronic computing has almost failed to cope with the international optical computation and communication traffic demand. Thanks to the non-linear material (NLM) which pave the way to new designs of new optical devices. A proposal for developing the most basic element in the optical computer such as optical switch, optical gates like OR gate, AND gate, XOR gate, flip-flops…. etc. has been introduced in recent research papers, also a proposal of the optical logic and arithmetic processor (OLAP) and the all-optical a-stable multi-vibrator has been introduced. Here some proposal developments are presented in this track, three components which they are most important in any new optical project those are optical switch, optical oscillator, and optical trap, the optical oscillator was introduced using an electro-optical modulator and, in this study, the oscillator design has no electro-optical elements, also the optical trap here works as an optical memory of binary data.

ZH: A Complete Graphical Calculus for Quantum Computations Involving Classical Non-linearity

Abstract: We present a new graphical calculus that is sound and complete for a universal family of quantum circuits, which can be seen as the natural string-diagrammatic extension of the approximately (real-valued) universal family of Hadamard+CCZ circuits. The diagrammatic language is generated by two kinds of nodes: the so-called 'spider' associated with the computational basis, as well as a new arity-N generalisation of the Hadamard gate, which satisfies a variation of the spider fusion law. Unlike previous graphical calculi, this admits compact encodings of non-linear classical functions. For example, the AND gate can be depicted as a diagram of just 2 generators, compared to ~25 in the ZX-calculus. Consequently, N-controlled gates, hypergraph states, Hadamard+Toffoli circuits, and diagonal circuits at arbitrary levels of the Clifford hierarchy also enjoy encodings with low constant overhead. This suggests that this calculus will be significantly more convenient for reasoning about the interplay between classical non-linear behaviour (e.g. in an oracle) and purely quantum operations. After presenting the calculus, we will prove it is sound and complete for universal quantum computation by demonstrating the reduction of any diagram to an easily describable normal form.

29.1 A 28nm Bulk-CMOS 4-to-8GHz ¡2mW Cryogenic Pulse Modulator for Scalable Quantum Computing

Abstract: While quantum processors are typically cooled to $\lt 25$ mK to avoid thermal disturbances to their delicate quantum states, all qubits still suffer decoherence and gate errors. As such, quantum error correction is needed to fully harness the power of quantum computing (QC). Current projections indicate that $\gt 1,000$ physical qubits will be required to encode one error-corrected qubit [1]. Implementing a system with 1,000 error-corrected qubits will likely require moving from the contemporary paradigm where control and readout of the quantum processor is carried out using racks of room temperature electronics to one in which integrated control/readout circuits are located within the cryogenic environment and connected to the quantum processor through superconducting interconnects [2]. This is a major challenge, as the cryo ICs must be high performance and very low power (eventually $\lt 1$ mW/qubit). In this paper, we report the design and system-level characterization of a prototype cryo-CMOS IC for performing XY gate operations on transmon (XMON) qubits.

2D-FDTD simulation of ultra-compact multifunctional logic gates with nonlinear photonic crystal

Abstract: In the present paper, we aim to report an ultra-compact AlGaAsκ(3) photonic crystal structure to realize multifunctional logic responses. The properties of the proposed model are numerically investigated with different physical parameters by the 2D-finite difference time domain (FDTD) method. For this purpose, the effect of the geometrical parameters and dielectric materials, including Si and InSb, in the near-infrared region are studied. To obtain dynamical tunability of the proposed model, the effect of the defects is then utilized. Numerical results show that the proposed devices are able to operate as multifunctional logic devices including an AND gate and a demultiplexer. Moreover, the structure has a compact footprint of 8.85 μm×8.85 μm×100 nm. We expect that this theoretical result leads to remarkable applications in photonic integrated circuits, e.g., optical memory.

Neural Logic Machines

Abstract: We propose the Neural Logic Machine (NLM), a neural-symbolic architecture for both inductive learning and logic reasoning. NLMs exploit the power of both neural networks---as function approximators, and logic programming---as a symbolic processor for objects with properties, relations, logic connectives, and quantifiers. After being trained on small-scale tasks (such as sorting short arrays), NLMs can recover lifted rules, and generalize to large-scale tasks (such as sorting longer arrays). In our experiments, NLMs achieve perfect generalization in a number of tasks, from relational reasoning tasks on the family tree and general graphs, to decision making tasks including sorting arrays, finding shortest paths, and playing the blocks world. Most of these tasks are hard to accomplish for neural networks or inductive logic programming alone.

Novel forksheet device architecture as ultimate logic scaling device towards 2nm

Abstract: To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.

High-efficiency and integrable DNA arithmetic and logic system based on strand displacement synthesis

Abstract: Powerful information processing and ubiquitous computing are crucial for all machines and living organisms. The Watson-Crick base-pairing principle endows DNA with excellent recognition and assembly abilities, which facilitates the design of DNA computers for achieving intelligent systems. However, current DNA computational systems are always constrained by poor integration efficiency, complicated device structures or limited computational functions. Here, we show a DNA arithmetic logic unit (ALU) consisting of elemental DNA logic gates using polymerase-mediated strand displacement. The use of an enzyme resulted in highly efficient logic gates suitable for multiple and cascaded computation. Based on our basic single-rail DNA configuration, additional combined logic gates (e.g., a full adder and a 4:1 multiplexer) have been constructed. Finally, we integrate the gates and assemble the crucial ALU. Our strategy provides a facile strategy for assembling a large-scale complex DNA computer system, highlighting the great potential for programming the molecular behaviors of complicated biosystems. Current DNA computational systems are constrained by integration efficiency, device structures and limited functions. Here the authors design a DNA arithmetic logic unit that uses polymerase-mediated strand displacement.

All-optical logic gates based on nanoring insulator–metal–insulator plasmonic waveguides at optical communications band

Abstract: We propose, analyze, and simulate a configuration to realize all-optical logic gates based on nanoring insulator–metal–insulator (IMI) plasmonic waveguides. The proposed plasmonic logic gates are numerically analyzed by finite element method. The analyzed gates are NOT, OR, AND, NOR, NAND, XOR, and XNOR. The operation principle of these gates is based on the constructive and destructive interferences between the input signal(s) and the control signal. The suggested value of transmission threshold between logic 0 and logic 1 states is 0.25. The suggested value of the transmission threshold achieves all seven plasmonic logic gates in one structure. We use the same structure with the same dimensions at 1550-nm wavelength for all proposed plasmonic logic gates. Although we realize seven gates, in some cases, the transmission of the proposed plasmonic logic gates exceeds 100%, for example, in OR gate (175%), in NAND gate (112.3%), and in XNOR gate (175%). As a result, the transmission threshold value measures the performance of the proposed plasmonic logic gates. Furthermore, the proposed structure is designed with a very small area (400 nm × 400 nm). The proposed all-optical logic gates structure significantly contributes to the photonic integrated circuits construction and all-optical signal processing nanocircuits.

Integrated magnonic half-adder.

Abstract: Spin waves and their quanta magnons open up a promising branch of high-speed and low-power information processing. Several important milestones were achieved recently in the realization of separate magnonic data processing units including logic gates, a magnon transistor and units for non-Boolean computing. Nevertheless, the realization of an integrated magnonic circuit consisting of at least two logic gates and suitable for further integration is still an unresolved challenge. Here we demonstrate such an integrated circuit numerically on the example of a magnonic half-adder. Its key element is a nonlinear directional coupler serving as combined XOR and AND logic gate that utilizes the dependence of the spin wave dispersion on its amplitude. The circuit constitutes of only three planar nano-waveguides and processes all information within the magnon domain. Benchmarking of the proposed device is performed showing the potential for sub-aJ energy consumption per operation.

Difference in Device Temperature Determination Using p-n-Junction Forward Voltage and Gate Threshold Voltage

Abstract: Determination of chip temperature is a key element in the lifetime estimation of power devices. There are several temperature sensitive electrical parameters for this purpose, which allow accurate measuring of the chip temperature on fully packaged devices. Among all these parameters, the forward voltage of a p-n junction is probably the most widely used parameter for temperature determination of a power semiconductor device. In metal-oxide-semiconductor (MOS) gated power semiconductor devices, gate threshold voltage is an alternative parameter with high temperature resolution. In this paper, the p-n-junction forward voltage and the gate threshold voltage of MOS-gated power devices were investigated. The difference between temperature measurements via the two methods was analyzed.

MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper

Abstract: Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Abstract: Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our approach is fully automatic and exploits cut enumeration algorithms to explore optimization potentials in local subcircuits. The experimental results show that our approach can reduce the number of AND gates by 34% on average compared to generic size optimization algorithms. Further, we are able to reduce the number of AND gates up to 76% in best-known benchmarks from the cryptography community.

Graphene Nanoribbon Based Complementary Logic Gates and Circuits

Abstract: As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thereby prompting for conducting research on new materials, devices, and/or computation paradigms. Within this context, graphene nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic structures for carbon-based nanoelectronics. In this paper, we make use of the fact that GNR behavior can be modulated via top/back gate contacts to mimic a given functionality and combine complementary GNRs for constructing Boolean gates. We first introduce a generic gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing its complement. Then, we seek GNR dimensions and gate topologies required for the design of 1-, 2-, and 3-input graphene-based Boolean gates, validate the proposed gates by means of SPICE simulation, which makes use of a non-equilibrium Green's function Landauer formalism based Verilog-A model to calculate GNR conductance, and evaluate their performance with respect to propagation delay, power consumption, and active area footprint. Simulation results indicate that, when compared with 7 nm FinFET CMOS counterparts, the proposed gates exhibit $\text{6}\times$ to 2 orders of magnitude smaller propagation delay, 2 to 3 orders of magnitude lower power consumption, and necessitate 2 orders of magnitude smaller active area footprint. We further present full adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of error correcting codes codecs, which outperforms the CMOS equivalent carry-out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits $\text{6.2}\times$ smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area, when compared with the 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based $n$ -bit ripple carry adder, whose performance is linear in the carry-out path, will be $\text{108}\times$ faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to dc-noise characteristics, while performance-wise has a $\text{3.6}\times$ smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue toward future competitive carbon-based nanoelectronics.

Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch

Abstract: The hybrid switch (HyS) of a higher-current main Si IGBT and a parallel lower-current auxiliary Silicon Carbide (SiC) mosfet offer an improved cost/performance tradeoff for practical power electronic designs. The purpose of this paper is to investigate the short-circuit (SC) ruggedness, failure mechanisms, and techniques for improvement of the Silicon/SiC HyS. The influence of major limiting factors, including dc bus voltage, gate drive voltage, gate control pattern, case temperature, and SiC mosfet sizing are experimentally studied. Two SC failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC mosfet are identified using microscopic failure analysis techniques. An optimum gate control selection is proposed to improve the HyS's SC withstanding time with minimum increase in its power loss.

Clockless Dynamic SFQ and Gate With High Input Skew Tolerance

Abstract: We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ) logic. We have successfully designed and tested a 2-input DSFQ and gate and showed its ability to hold dynamically its internal states for over 25 ps while operating at 10 GHz clock frequency. We also demonstrated picosecond-scale dynamics of DSFQ circuit with an on-chip Josephson sampler, with only low-speed interfaces required.

Multifunctional anti-ambipolar p-n junction based on MoTe2/MoS2 heterostructure

Abstract: The discovery of atomically thin two-dimensional materials enables building numerous van der Waals heterostructures with original and promising properties for potential electronic and optoelectronic applications. Among them, the antiambipolar characteristic is one of the most appealing ones, which refers to the inverse “V” shape of the transfer curve of the heterojunction. As a result, it is expected to implement various important logic functions, such as double-frequency and multivalue. In this work, we modulated an ambipolar MoTe2/MoS2 heterojunction to show prominent antiambipolar behavior by simply annealing the device at elevated temperature. The on-off ratio and on-state current of the antiambipolar characteristic can be tuned as large as 106 and approximately microamperes, respectively, by optimizing the annealing temperature. Furthermore, we preliminarily demonstrated a self-powered photodetector and a ternary inverter based on this device. The photodetector showed a short-current circuit and an open-circuit voltage of 0.4 μA and 7.5 mV, respectively, at incident light intensity of 2.54 mW/cm2, and gate tunable photocurrent ranging from 0 to 380 pA under zero source-drain bias. The ternary inverter can output three distinct values varying on the order of subvolt as the input voltage (gate bias) ranges from −60 V to 60 V.

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing.

Abstract: In this paper, electrostatically configurable 2D tungsten diselenide (WSe2 ) electronic devices are demonstrated. Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a metal-oxide-semiconductor field-effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self-consistent full-band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub-60 mV dec-1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

Logic Sensing of MicroRNA in Living Cells Using DNA-Programmed Nanoparticle Network with High Signal Gain

Abstract: Molecular circuits capable of implementing Boolean logic in cellular environments have emerged as an important tool for in situ sensing, elucidating, and modulating cell functions. The performance of existing molecular computation devices in living cells is limited because of the low level of biomolecular inputs and moderate signal gain. Herein, we devised a new class of DNA-programmed nanoparticle network with integrated molecular computation and signal amplification functions for logic sensing of dual microRNA (miRNA) molecules in living cells. The nanoparticle network, which is composed of DNA-bridged gold nanoparticles and quantum dots (QDs), could simultaneously interface with two miRNA molecules, amplify the molecular inputs, perform a calculation through AND logic gate, and generate QD photoluminescence (PL) as an output signal. Significant improvement in imaging sensitivity is achieved by integrating the signal amplifier into the molecular computation device. It allows discrimination of specific c...

Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

Abstract: In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET to enhance the device reliability Dual Metal Dielectric Engineered Gate All Around (DMDEGAA) MOSFET has been compared with both cylindrical Dual Metal Gate All Around (DMGAA) MOSFET and cylindrical Gate All Around (GAA) MOSFET DMDEGAA MOSFET has larger tunneling distance than other two devices which further reduces Band To Band Tunneling (BTBT) It reduces GIDL current over other devices directing immunity from the leakages along with higher Ion/Ioff ratio showing larger applicability for digital applications DMDEGAA MOSFET shows Subthreshold Slope (SS) close to 60 mV/decade and has higher transconductance (gm), higher Transconductance Generation Factor (TGF), higher early voltage (VEA), lower channel resistance (Rch), higher Current Gain (CG) and higher Maximum Transducer Power Gain (MTPG) for improved analog performance DMDEGAA MOSFET also poses higher Cut Off Frequency (fT), higher Frequency Transconductance Product (FTP) and lower Total Gate Capacitance (Cgg) showing its efficacy for high speed and high frequency applications

Piezophototronic gated optofluidic logic computations empowering intrinsic reconfigurable switches.

Abstract: Optofluidic nano/microsystems have advanced the realization of Boolean circuits, with drastic progression to achieve extensive scale integration of desirable optoelectronics to investigate multiple logic switches. In this context, we demonstrate the optofluidic logic operations with interfacial piezophototronic effect to promote multiple operations of electronic analogues. We report an optofluidic Y-channeled logic device with tunable metal-semiconductor-metal interfaces through mechanically induced strain elements. We investigate the configuration of an OR gate in a semiconductor-piezoelectric zinc oxide nanorod-manipulated optofluidic sensor, and its direct reconfiguration to logic AND through compressive strain-induced (−1%) piezoelectric negative polarizations. The exhibited strategy in optofluidic systems implemented with piezophototronic concept enables direct-on chip working of OR and AND logic with switchable photocurrent under identical analyte. Featured smart intrinsic switching between the Boolean optoelectronic gates (OR↔AND) ultimately reduces the need for cascaded logic circuits to operate multiple logic switches on-a-chip. Designing optofluidic nano/microsystems to realize large-scale Boolean circuits remains a challenge. Here, the authors propose a flexible optofluidic framework to perform binary computations with an integrated piezophototronic mechanism controlling the optofluidic switching of logic gates (PPOF).