AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Abstract: An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

Symmetric self-electrooptic effect device: optical set-reset latch, differential logic gate, and differential modulator/detector

Abstract: The symmetric self-electrooptic-effect device (S-SEED), a structure consisting of two p-i-n diodes electrically connected in series and acting as an optically bistable set-reset latch, is discussed. Applications and extensions of this device are also discussed. The devices do not require the critical biasing that is common to most optically bistable devices and thus is more useful for system applications. They have been optically cascaded in a photonic ring counter and have been used to perform different NOR, OR, NAND, and AND logic functions. Using the same device, a differential modulator that generates a set of complementary output beams with a single voltage control lead and a differential detector that gives an output voltage dependent on the ratio of the two optical input powers have been demonstrated. >

Tunneling Field-Effect Transistor: Capacitance Components and Modeling

Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.