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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


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Patent
10 Dec 1990
TL;DR: In this paper, a video signal processor includes two eight-bit adders, each of which has a carry-in input terminal and a carryout output terminal, selectively coupled via an AND gate.
Abstract: A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuiry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

45 citations

Journal ArticleDOI

45 citations

Patent
24 Oct 1997
TL;DR: In this paper, a method for forming a MOSFET transistor using a disposable gate (120) is described, where the gate dielectric (110) and gate electrode (112) are then formed.
Abstract: A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

44 citations

Journal ArticleDOI
TL;DR: In this article, a class of downstream-water-level feedback canal controllers was described, and several controllers within this class were tuned with the same quadratic performance criteria (i.e., identical penalty functions for optimization).
Abstract: In a companion paper, a class of downstream-water-level feedback canal controllers was described. Within this class, a particular controller is chosen by selecting which controller coefficients to optimize (tune), the remaining coefficients being set to zero. These controllers range from a series of simple proportional-integral (PI) controllers to a single centralized controller that considers lag times. In this paper, several controllers within this class were tuned with the same quadratic performance criteria (i.e., identical penalty functions for optimization). The resulting controllers were then tested through unsteady-flow simulation with the ASCE canal automation test cases for canal 1. Differences between canal and gate properties, as simulated and as assumed for tuning, reduced controller performance in terms of both water-level errors and gate movements. The test case restrictions placed on minimum gate movement caused water levels to oscillate around their set points. This resulted in steady-state errors and much more gate movement (hunting). More centralized controllers handle unscheduled flow changes better than a series of local PI controllers. Controllers that explicitly account for pool wave travel times did not improve control as much as expected. Sending control actions within a given pool to upstream pools improved performance, but caused oscillations in some cases, unless control signals were also sent downstream. A good compromise between controller performance and complexity is provided by controllers that pass feedback from a given water level to the check structure at the upstream end of its pool (i.e., that used for downstream control of an individual pool) and to all upstream and one downstream check structures.

44 citations

Journal ArticleDOI
TL;DR: In this article, the authors leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit fulladder (FA) circuit.
Abstract: Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 $\mu \text{A}$ to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively.

44 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372