AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Liquid crystal display and method for driving the same

Abstract: A liquid crystal display (LCD) and a method for driving the same are provided. The LCD includes a liquid crystal panel divided into a plurality of panel regions having data lines and gate lines arranged two-dimensionally; gate drivers that correspond to the panel regions, are independently driven, and alternately supply gate signals to the corresponding panel regions; a data driver supplying data signals to the data lines; and a backlight unit radiating light to the liquid crystal panel. Accordingly, color mixing can be substantially prevented by changing the transmission mode of gate signals.

All-optical photonic crystal logic gates using nonlinear directional coupler

Abstract: In this paper, a nonlinear photonic crystal structure consisting of a nonlinear directional coupler and junctions for the design of all-optical logic gates is proposed. A bi-functional photonic crystal structure is initially designed which provides different two XOR or OR logic operations. Thereafter, by applying some modifications in the basic structure, new topologies for all-optical XNOR, NOR and AND logic gates are proposed. Nonlinear rods of the proposed structure are made of silicon nanocrystal to create required phase shift. The finite difference time domain and plane wave expansion methods are used to evaluate the proposed structures. Our simulation results show that the proposed gates can operate with a bit rate of more than 1 Tbits/s and also, inputs and output of the proposed logic gates are homogeneous with the required power of 3W for switching operation.

Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

Abstract: Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets T/sub UTS/ such that each C(n) has a unique test set T(n) in T/sub UTS/ that detects all F-type faults in every member of C(n). We show that if k /spl ges/ 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n/sup 2/ + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.

Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory

Abstract: A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.