AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Method for forming a MOSFET with substrate source contact

Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N + , N-,P-, N + regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N + interface. A buried P-, N + short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N + substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Monte Carlo analysis of dynamic and noise performance of submicron MOSFETs at RF and microwave frequencies

Abstract: In this paper, an ensemble 2D bipolar Monte Carlo simulator is employed for the study of static characteristics, high-frequency response and noise behaviour in a 0.3 µm gate-length n-MOSFET in common source configuration. Short-channel effects, such as velocity overshoot in the pinch-off region, together with the appearance of hot electrons at the drain end of the channel are observed in the static characteristics. Admittance parameters and the small-signal equivalent circuit have been calculated in order to characterize the dynamic response of the device. The use of a bipolar simulator allows one to study the dynamics of both types of carriers simultaneously. While the static results are dominated by the electron transport, the contribution of holes mainly affects the drain-substrate capacitive coupling. The noise behaviour of the simulated MOSFET is also studied (up to 40 GHz) by means of different parameters, such as the spectral densities of the current fluctuations at the drain and gate terminals (and their cross-correlation), normalized α, β and C parameters and NFmin . In the saturation regime, due to the presence of hot carriers, an increase in drain and gate noise with respect to the long-channel prediction has been found. Moreover, a stronger correlation between drain and gate noise is observed, especially at low drain current. Induced gate noise is found to play a crucial role in the determination of NFmin at high drain currents.

A power supply circuit for gate driver of GaN-based flying capacitor multi-level converters

Abstract: Recently, flying capacitor multi-level (FCML) converters with GaN power switches have received increased attention due to their potential to achieve high efficiency and high power density. However, one of the major challenges is providing power to the gate drive circuits, most of which are not ground referenced. The most common existing method utilizes isolated DC/DC converters, which are bulky, expensive and energy inefficient. This work introduces two new techniques that leverage inherent properties of the FCML topology and the GaN switches to provide gate drive power to the floating switches with minimum hardware requirements. The two methods, termed cascaded bootstrap and gate driven charge pump, are analyzed in details and their performance evaluated. A new power supply circuit combining the two techniques can help shrink the size of the converter, and further increase the converter's power density. Experimental results show that the proposed circuit is up to 5× more power efficient than conventional solutions, at 1/10 of the cost.

Advantages of heterogeneous logic block architecture for FPGAs

Abstract: The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA.

Counter emf commutated self-starting brushless d.c. motor

Abstract: The stator windings of a brushless DC motor are energized through individual silicon controlled rectifiers arranged in a ring counter circuit which is triggered from a pulse source. When the motor is to be started, an AND gate forces the first pulse to trigger a specific silicon controlled rectifier. The AND gate then permits subsequent pulses to be steered to various silicon controlled rectifiers in the desired sequence. The pulse source is synchronized through an OR gate coupled to receive signals from each stator winding. When a given silicon controlled rectifier is turned off, the corresponding stator winding is deenergized. The motion of the rotor, however, induces a counter EMF in the deenergized winding. This counter EMF is applied through the OR gate to synchronize the pulse source.