AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Detail study of SiC MOSFET switching characteristics

Abstract: This paper makes detail study of the latest SiC MOSFETs switching characteristics in relation to gate driver maximum current, gate resistance, common source inductance and parasitic switching loop inductance The switching performance of SiC MOSFETs in terms of turn on and turn off voltage and current are presented Switching losses analysis is made according to the experiment results The switching characteristics study and switching losses analysis could give some guidelines of gate driver IC and gate resistance selection, switching losses estimation and circuit design of SiC MOSFETs

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

Abstract: The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >

Simultaneous voltage scaling and gate sizing for low-power design

Abstract: This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltage-scaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23% to 57% over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages.

Buffered routing element for a user programmable logic device

Abstract: A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.