AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Multicell battery system with individually controllable cell bypasses

Abstract: A multicell battery system includes at least two battery cells, and a selective cell bypass for each of the battery cells. Each cell bypass includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a source, a drain, and a gate, a first electrical interconnection from the MOSFET source to a first side of the battery cell, a second electrical interconnection from the MOSFET drain to a second side of the battery cell, and an activation circuit connected to the MOSFET gate. The activation circuit includes an AND gate having as one input an AC square wave signal and as a second input a selection signal, a capacitor connected to the AND gate output signal, and a cascade voltage doubling circuit having an input in communication with a second electrode of the capacitor and an output in communication with the MOSFET gate.

Method of forming a MOSFET using a disposable gate with a sidewall dielectric

Abstract: A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222,223, and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g., using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214). The disposable gate (220) is then removed and the gate dielectric (210) and gate electrode (212) are formed.

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

Abstract: The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.

Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm

Abstract: Ten years have passed since the beginning of graphene research. In this period we have witnessed breakthroughs both in fundamental and applied research. However, the development of graphene devices for mass production has not yet reached the same level of progress. The architecture of graphene field-effect transistors (FET) has not significantly changed, and the integration of devices at the wafer scale has generally not been sought. Currently, whenever an electrolyte-gated FET (EGFET) is used, an external, cumbersome, out-of-plane gate electrode is required. Here, an alternative architecture for graphene EGFET is presented. In this architecture, source, drain, and gate are in the same plane, eliminating the need for an external gate electrode and the use of an additional reservoir to confine the electrolyte inside the transistor active zone. This planar structure with an integrated gate allows for wafer-scale fabrication of high-performance graphene EGFETs, with carrier mobility up to 1800 cm(2) V(-1) s(-1). As a proof-of principle, a chemical sensor was achieved. It is shown that the sensor can discriminate between saline solutions of different concentrations. The proposed architecture will facilitate the mass production of graphene sensors, materializing the potential of previous achievements in fundamental and applied graphene research.

Process for forming a T-shaped gate structure

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess. Gate contact metal is then deposited in the opening thus formed and the nitride, photoresist and gold layers are removed, lifting off a portion of the gate metal layer thus leaving a T-shaped gate which provides a minimum length at the channel gate interface and provides a low gate resistance.