AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Nanowire systems: technology and design

Abstract: Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology.

A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

Abstract: A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson’s equation is solved in channel region by a method of series expansion similar to Green’s function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

High voltage tolerant CMOS input/output circuit

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal. A comparison and logic control circuit is coupled to the power supply terminal and to the conductor, and is configured to compare a supply voltage level to the input signal and is configured to generate an affirmative logic signal when the input signal is greater than the supply voltage level and to generate a negative logic signal when the input signal is less than the supply voltage level. An N-well control circuit is coupled to the power supply terminal, to the conductor and to the pull-up circuit, where the N-well control circuit is responsive to the logic signal, and is configured to output a control N-well signal to control the PMOS transistor N-well voltage.

Resistor coupled Josephson logic

Abstract: A resistor coupled Josephson logic (RCJL) family, composed of OR, AND, and 2/3 majority gates, is proposed. The RCJL family consists of multiple Josephson junctions and resistors, and employs current injected switching. OR gates have I‐O isolation capability with high input sensitivity and wide operating current margin. In the AND gate, current margin as wide as the CIL AND gate and higher input sensitivity can be achieved without inductors. Experimental verification of the RCJL family operation is also described.

Bidirectional threshold voltage shift and gate leakage in 650 V p-GaN AlGaN/GaN HEMTs: The role of electron-trapping and hole-injection

Abstract: The threshold voltage (V TH ) instability of a 650 V p-GaN gate AlGaN/GaN HEMTs and its underlying physical mechanism was investigated by forward gate stress. A uniquely bidirectional shift in the V TH with the critical gate voltage V critical of 6 V was observed in the device after the static and dynamic gate stress. The temperature- and time-dependent gate leakage current revealed that the occurrence of electron-trapping and hole-injection in sequence with the increasing gate bias responsible for the inhomogeneous shift in V TH . At small positive gate bias (Vg TH is induced by electron filling of acceptor-like traps in AlGaN barrier, while the gate leakage is accordingly dominated by trap-dominated SCLC. At large positive gate bias (V G >6V), the hole-injection is triggered that results in a negative shift in V TH and the gate leakage exhibits a substantial increase due to the forward turn on of the gate pn junction. Besides, the effective hole-injection also leads to a significant increase in OFF-state drain leakage, which is believed to be the pronounced electron-hole recombination in the channel.