AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce the capacitance of the gate of the semiconductor device, and to stabilize electrical characteristics by preventing the stacking of a source-drain impurity to the gate and self-aligning the gate and a drain. CONSTITUTION:A gate oxide film 5 is formed, poly Si is shaped onto the whole surface, the N type impurity is diffused and a conductor is formed, and gate metals 4, 4' are shaped lest source regions 11a, 12b and drain regions 11b, 12a should be stacked. Resists 13 are left, and a PMOS transistor region is masked, and impurity regions 14a, 14b with the same conduction type as the source region 12b and the drain region 12a are molded through ion implantation. The positions of the source region 12b, the drain region 12a and the gate metal 4' are determined in a self-alignment manner at the time. Impurity regions 17a, 17b with the same conduction type as the regions 11a, 11b are shaped into an NMOS transistor region through a mask-ion implantation method. Since the quantity of the impurity dosed for shaping the impurity regions 17a, 17b, 14a, 14b is little, the impurity does not penetrate the gate, and VTH does not change.

Dynamically reconfigurable processor

Abstract: Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor. Furthermore, disclosed is a dynamically reconfigurable processor, which is reconfigurable using the generated logic circuit configuration information. Associated methods are also disclosed.

Storage cell for nonvolatile electrically alterable memory

Abstract: A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.

Independently controlled, double gate nanowire memory cell with self-aligned contacts

Abstract: A doubled gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.