AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Gate oxide scaling limits and projection

Abstract: MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient for MOSFET scaling to 0.05 /spl mu/m.

An ultrafast all-optical gate

Abstract: We present a new ultrafast optical waveguide gate based on a nonlinear optical interaction in a waveguide interferometer. A train of signal pulses is gated by control pulses which change the refractive index in only one arm of the interferometer. The principle of operation is demonstrated using a modified Mach-Zehnder interferometer, 2 cm long, fabricated in a LiNbO 3 substrate. The experiments were performed with a near-infrared dye laser which produced 5 ps pulses at \lambda = 840 nm. A maximum modulation on the order of 10-3was obtained for a peak control power of 2 W. Experimentally, we determined the appropriate nonlinear coefficient of LiNbO 3 to be n_{2} = 3 \times 10^{-9} (MW/cm2)-1. As possible applications of the structure we describe an all-optical inverter, an XOR gate, and an AND gate. We conclude with a brief description of a random number generator encoder and decoder based on a few all-optical logic gates.

Logic-Based Methods for Optimization

Abstract: This paper proposes a logic-based approach to optimization that combines solution methods from mathematical programming and logic programming. From mathematical programming it borrows strategies for exploiting structure that have logic-based analogs. From logic programming it borrows methods for extracting information that are unavailable in a traditional mathematical programming framework. Logic-based methods also provide a unified approach to solving optimization problems with both quantitative and logical constraints.

Flash memory with high-K dielectric material between substrate and gate

Abstract: A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

Abstract: The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.