Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: In this paper, a layer-by-layer growth of wafer-scale GaTe with a high hole mobility of 28.4 cm2/(V·s) by molecular beam epitaxy was reported.
Abstract: Two-dimensional (2D) materials have attracted substantial attention in electronic and optoelectronic applications with the superior advantages of being flexible, transparent, and highly tunable. Gapless graphene exhibits ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit high sensitivity and tunable responsivity to visible light. However, the device yield and repeatability call for further improvement to achieve large-scale uniformity. Here, we report a layer-by-layer growth of wafer-scale GaTe with a high hole mobility of 28.4 cm2/(V·s) by molecular beam epitaxy. The arrayed p-n junctions were developed by growing few-layer GaTe directly on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and a high photovoltaic external quantum efficiency up to 62% at 4.8 µW under zero bias. The photocurrent reaches saturation fast enough to capture a time constant of 22 µs and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photoimages were acquired by the GaTe/Si photodiodes with reasonable contrast and spatial resolution, demonstrating the potential of integrating the 2D materials with silicon technology for novel optoelectronic devices.
36 citations
TL;DR: AlGaN/GaN High Electron Mobility Transistors with various gate lengths have been step-stressed under both on- and off-state conditions reveal that the Schottky contact is the source of degradation, and the electric field is the main mechanism for degradation.
36 citations
TL;DR: A two-stage approach to gate matrix layout is described and results show that the approach can achieve a considerable improvement compared to earlier algorithms, while satisfying additional constraints.
Abstract: A two-stage approach to gate matrix layout is described. The approach consists of: the determination of an optimal gate sequence and an assignment of nets to rows such that the nets are realizable. The gate sequence algorithm is based on T. Asano's approximate search (1981). Modifications are made to it to take into account constraints of transistor sizing, serial subcircuit conflicts, input/output (I/O) gates, and I/O nets. The zone-net assignment algorithm assigns nets to a minimum number of rows determined by the gate sequence and provides a means to resolve vertical conflicts in the layout. Power connections are implemented using the power nets and possible added power rows. Results of examples show that the approach can achieve a considerable improvement compared to earlier algorithms, while satisfying additional constraints. >
36 citations
Patent•
19 Jun 2001
TL;DR: In this article, the gate capacity and drain capacity of these PMOS transistors are appended to the two nodes, and the gate and drain capacities of these transistors were analyzed.
Abstract: The SRAM memory cell comprises two inverters connected in complement with each other. Each inverter comprises one NMOS transistor and one PMOS transistor. Gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. Drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. Drain of an another PMOS transistor and gate of still another PMOS transistor are connected to the first node. Drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacity and drain capacity of these PMOS transistors is appended to the two nodes.
36 citations
TL;DR: It is shown that using multilevel signaling technique in such a system results to the performance improvement, and the numerical closeness between the analytical and system simulation reveals the tightness of the obtained upper bound, hence making them quite useful in evaluating the above system's performance.
Abstract: In this paper, we present a novel multirate, differentiated quality of service (QoS) optical CDMA (OCDMA) system using multilevel signaling technique. The emphasis is on OCDMA systems employing multi-length variable-weight optical orthogonal codes (MLVW-OOC) as signature sequence. We begin by presenting a two-class variable-weight OCDMA system in which all users have the same energy level in one bit duration. As a consequence, high weight users transmit their corresponding optical pulses at a lower power while low weight users transmit their corresponding optical pulses at a higher power level. We show that using this multilevel signaling technique, while employing the well known optical AND logic gate receiver structure, we achieve a considerable improvement in the performance of low-weight (high-power) users while the performance of high-weight (low-power) users not altered in comparison to one-level system. In the next step, we indicate that by using the recently introduced multistage receiver structure, which employs advanced optical logic gate elements, interferences at different power levels are distinguishable so that the performance of both high-weight and low-weight users are improved. Furthermore, we employ multilevel signaling technique in OCDMA system based on MLVW-OOC (multirate, differentiated QoS system). We show that using multilevel signaling technique in such a system results to the performance improvement. To analyze the performance of the system we obtain a closed-form relation expressing an upper bound on the probability of error of the system. Finally, to validate the upper bound, the analytical results are compared to the results of system simulation. The numerical closeness between the analytical and system simulation reveals the tightness of the obtained upper bound, hence making them quite useful in evaluating the above system's performance.
36 citations