AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Abstract: This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60 percent compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.

Power conversion device

Abstract: The present invention aims to provide a power converter with an arm including switching devices connected in parallel, realizing long lifespans of switching devices. An inverter includes an upper and a lower arm, and gate drive circuits each driving the corresponding arm according to a gate control signal Gup_s indicating ON/OFF periods. Each arm includes switching devices connected in parallel. Each gate drive circuit includes: a switching gate control circuit 230 u bringing a switching device 210 u into conduction at the beginning of the ON period and bringing the same out of conduction within the ON period; and a conduction gate control circuit 231 u bringing switching devices 211 u and 212 u within a period from when the switching device 210 u is brought into conduction until the same is brought out of conduction, wherein the switching device 210 u has a lower parasitic capacitance than the switching devices 211 u and the 212 u.

Fast flush for a first-in first-out memory

Abstract: In a memory circuit including a write bit-line (32, 36) for writing data into a memory cell (10), and a read bit-line (34, 38) for reading data from the cell, a transistor (50, 52) is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied by an AND gate (44) to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.

A high-speed dynamic domino circuit implemented with GaAs MESFETs

Abstract: The dynamic domino and gates composed of GaAs depletion-mode (D-mode) MESFETs are described in this work. This circuit allows very complex input combinational functions which can provide very high gate equivalences. Test circuits were designed which consisted of chains of 15 dynamic AND gates with static off-chip drivers. The circuits were fabricated by a foundry and tested at the wafer level. The measured propagation delay per gate is 180 ps for a two-input AND gate and 220 ps for a four-input AND gate, with a power consumption of 0.55 mW/gate. The minimum frequency of operation is found to be as low as 100 kHz. A 4-b carry generator was designed and simulated. A delay of 400 ps was predicted for this circuit.

Enzymatic AND Logic Gate with Sigmoid Response Induced by Photochemically Controlled Oxidation of the Output

Abstract: We report a study of a system which involves an enzymatic cascade realizing an AND logic gate, with an added photochemical processing of the output allowing to make the gate's response sigmoid in both inputs. New functional forms are developed for quantifying the kinetics of such systems, specifically designed to model their response in terms of signal and information processing. These theoretical expressions are tested for the studied system, which also allows us to consider aspects of biochemical information processing such as noise transmission properties and control of timing of the chemical and physical steps.