AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Adjustable output driver circuit

Abstract: An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.

Molecule-based photonically switched half-adder.

Abstract: A molecule-based binary half-adder with optical inputs and outputs has been demonstrated. The half-adder consists of two photochromic organic molecules in solution and a third-harmonic-generating crystal. One substance acts as an AND Boolean logic gate and the other as an XOR gate. Inputs are laser pulses at 1064 or 532 nm that initiate photoisomerization reactions. Outputs are the optical absorbance of a fullerene radical anion (AND gate) and fluorescence of a porphyrin (XOR gate). The system carries out binary addition based on the laser input pulses. Half-adders in combination are capable of carrying out all mathematical operations necessary for digital computing.

Logic cell for field programmable gate array having optional internal feedback and optional cascade

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Reversible Logic Circuits Made of DNA

Abstract: We report reversible logic circuits made of DNA. The circuits are based on an AND gate that is designed to be thermodynamically and kinetically reversible and to respond nonlinearly to the concentrations of its input molecules. The circuits continuously recompute their outputs, allowing them to respond to changing inputs. They are robust to imperfections in their inputs.

Design procedures for differential cascode voltage switch circuits

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.