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AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: This work demonstrates two DNA-based logic circuits that behave as ahalf-adder and a half-subtractor, inspired by molecular beacons.
33 citations
TL;DR: In this article, a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices is presented, showing that the benefits of the selfaligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance.
Abstract: Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system
33 citations
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TL;DR: In this article, it was shown that the quantum N()T gate can achieve a fidelity of F = (N + 1)/(N + 2), which is equal to the fidelity of estimation of the input qubits.
Abstract: The action of a NOT gate on a classical bit results in a change of its value from a 0 to a 1 and vice versa. The action of the classical NOT gate is in principle perfect because with fidelity equal to unity it complements the value of a bit. The action of the quantum NOT gate in a computational basis |0) and |1) is very similar to the action of the classical N()T gate. However, a more general quantum mechanical operation which corresponds to a classical NOT gate would take a qubit in an arbitrary state |Ψ) and produce a qubit in the state |Ψ⊥) orthogonal to |Ψ). This operation is anti-unitary and therefore, cannot be realized exactly. So how well we can do? We find a unitary transformation acting on an input qubit and some auxiliary qubits, which represent degrees of freedom of the quantum NOT gate itself, which approximately realizes the NOT operation on the state of the original qubit. We call this 'device' a universal-NOT gate because the size of the error it produces is independent of the input state. We show that an optimal U-NOT gate which has as its input N identical qubits and produces M outputs achieves a fidelity of F = (N + 1)/ (N + 2), which is equal to the fidelity of estimation of the input qubits. We also show that when a priori information about the state of the input qubit is available, the fidelity of a quantum NOT gate can he much better than the fidelity of estimation.
33 citations
TL;DR: Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case, and up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate.
33 citations
Patent•
NEC1
TL;DR: In this paper, a simulation circuit for MOS transistors is provided in which neither oscillation nor a change in a characteristic of feedback capacitance occurs, and a ratio of a junction capacitance characteristic of the third diode and an electrostatic capacity characteristic of a capacitor is displayed, in a region where a voltage between the drain and gate is almost 0 (zero) V.
Abstract: A simulation circuit for MOS transistors is provided in which neither oscillation nor a change in a characteristic of feedback capacitance occurs. A ratio of a junction capacitance characteristic of a third diode and an electrostatic capacity characteristic of a capacitor to be displayed, changes in response to a change in a voltage between a drain and a gate and the junction capacitance characteristic of the third diode and the electrostatic capacity characteristic of the capacitor are displayed at an equal ratio in a region where a voltage between the drain and gate is almost 0 (zero) V and, therefore, normal simulation testing can be done and no oscillation occurs. Moreover, since no resistor component is connected in series in the third diode and the capacitor, there is no time constant. Therefore, a characteristic curve of the feedback capacitance can be normally obtained irrespective of the change rate of the voltage between the drain and gate.
33 citations