Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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TL;DR: This paper presents an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common sub expression elimination algorithms in literature.
33 citations
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IBM1
TL;DR: In this paper, a standard logic array can be electrically altered at different time intervals to execute complex logic functions, which can be personalized by implicant and logic networks, such as structure, time signals, personality signals, and any combination of (a), (b) and (c).
Abstract: A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine. The arrays can be produced, stockpiled and structurally personalized at a later time as required by a system designer. The method of operating the array is compatible with data processing machine programming and operation.
33 citations
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TL;DR: It is demonstrated both experimentally and theoretically that the analog noise generation by a single enzymatic logic gate can be dramatically reduced to yield gate operation with virtually no input noise amplification.
Abstract: In this work we demonstrate both experimentally and theoretically that the analog noise generation by a single enzymatic logic gate can be dramatically reduced to yield gate operation with virtually no input noise amplification. This is achieved by exploiting the enzyme's specificity when using a co-substrate that has a much lower affinity than the primary substrate. Under these conditions, we obtain a negligible increase in the noise output from the logic gate as compared to the input noise level. Experimental realizations of the AND logic gate with the enzyme horseradish peroxidase using hydrogen peroxide and two different co-substrates, 2,2'-azino-bis(3-ethylbenzthiazoline-6-sulphonic acid) (ABTS) and ferrocyanide, with vastly different rate constants confirmed our general theoretical conclusions.
33 citations
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25 Jul 2005TL;DR: In this article, the authors demonstrate an all-optical bit-wise 3-input AND gate using a single periodically-poled-lithium-niobate (PPLN) waveguide as a nonlinear optical element.
Abstract: We demonstrate an all-optical bit-wise 3-input AND gate using a single periodically-poled-lithium-niobate (PPLN) waveguide as a nonlinear optical element. Our module generates output '1' bits only when all inputs are '1', with negligible power penalty.
33 citations
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21 Jun 2009TL;DR: In this article, a high-reliability gate driving circuit includes a plurality of odd shift register stages and even shift register stage, where each odd-shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock.
Abstract: A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line.
33 citations