AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Exchange-based two-qubit gate for singlet-triplet qubits

Abstract: We analyze a simple exchange-based two-qubit gate for singlet-triplet qubits in gate-defined semiconductor quantum dots that can be implemented in a single exchange pulse. Excitations from the logical subspace are suppressed by a magnetic field gradient that causes spin-flip transitions to be non-energy-conserving. We show that the use of adiabatic pulses greatly reduces leakage processes comapred to square pulses. We also characterize the effect of charge noise on the entanglement fidelity of the gate both analytically and in simulations; demonstrating high entanglement fidelities for physically realistic experimental parameters. Specifically we find that it is possible to achieve fidelities and gate times that are comparable to single-qubit states using realistic magnetic field gradients.

Asymmetric field effect transistor structure and method

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Mechanisms for low-frequency oscillations in GaAs FET's

Abstract: Low-frequency oscillations in GaAs MESFET's were observed under back-gating conditions. The FET oscillations are directly related to oscillations in leakage currents in the semi-insulating GaAs substrate. The occurrence of these oscillations in the substrate is strongly dependent upon GaAs material. It is proposed that oscillating substrate leakage currents modulate the FET current in two ways; first, by modulating the active channel-substrate junction and second, by inducing periodic voltage fluctuations on the gate via gate pad contacts on the semi-insulating substrate. The latter mechanism is dominant and dependent upon gate bias and gate impedance.

Gate driver optimization to mitigate shoot-through in high-speed switching SiC half bridge module

Abstract: The high-speed switching of SiC MOSFET allows power converter to operate with higher frequency and lower switching loss. However, it tends to aggravate dv/dt effect due to the impact of parasitic parameters, resulting in shoot-through and high device stress in the half bridge configuration. In this study, a compact and high-speed gate driver is developed and optimized for SiC half bridge module. The impact of various circuit parameters including Miller capacitance, common source inductance, gate resistance and gate inductance is evaluated. The improved gate drivers with additional features are compared and optimized to eliminate shoot-through.

Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

Abstract: For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.