AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Complementary Logic Gate Arrays Based on Carbon Nanotube Network Transistors

Abstract: An efficient technique of fabricating high performance n- and p- type single-walled carbon nanotube (SWNT) network field-effect transistors (NET-FETs) is successfully demonstrated. Complementary inverters, NOR, NAND, OR, AND logic gates have been achieved from integrating these p- and n-type SWNT-NET-FETs. The processing technique described here is fully compatible with conventional silicon microelectronic technologies and it is readily suitable for scalable integration.

Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory

Abstract: Due to their CMOS compatibility, hafnium oxide based ferroelectric field-effect transistors (FeFET) gained remarkable attention recently, not only in the context of nonvolatile memory applications but also for being an auspicious candidate for novel combined memory and logic applications. In addition to bringing nonvolatility into existing logic circuits (Memory-in-Logic), FeFETs promise to guide the way to compact Logic-in-Memory solutions, where logic computations are examined in memory arrays or array-like structures. To increase the area-efficiency of such circuits, a dense integration of FeFETs and standard FETs is essential. In this paper, we show that the ultra-dense co-integration of FeFETs and nFETs (28nm HKMG) with shared active area does not alter the FeFET’s switching behavior, nor does it affect the baseline CMOS. Based on this, we propose the integration of a FeFET-based, 2-input look-up table (memory) directly into a 4-to-1 multiplexer (logic), which is utilized directly in a 2TNOR memory array or stand-alone circuit. The latter one dramatically reduces the transistor count by at least 33% compared to similar FeFET-based circuits. By storing values of the look-up table in a nonvolatile manner, no energy is consumed during standby mode, which enables normally-off computing. To take another step towards novel Logic-in-Memory designs, we experimentally demonstrate a very compact in-array 2T half adder and simulate an array-like 14T full adder, which exploit the advantages of the array arrangement: easy write procedure and a very compact, robust design. The proposed circuits exhibit energy-efficiency in the (sub)fJ-range and operation speeds of 1GHz.

Checking Delay-Insensitivity: 104 Gates and Beyond

Abstract: Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT)-solvers and is successfully tested on realistic design examples having tens of thousands of gates.

Redundant recording system with parity checking

Abstract: 1,020,479. Checking arrangements for datastorage apparatus. RADIO CORPORATION OF AMERICA. Feb. 10, 1964 [Feb. 25, 1963], No. 5531/64. Heading G4C. In a data storage system, errors are reduced by recording the input information twice; on playback checking the parities of both sets of reproduced signals; and when only one parity is correct selecting only the corresponding set of reproduced signals but when neither parity is correct selecting both sets of reproduced signals. As described, binary data to be recorded on a magnetic tape (or drum) 9 is applied over leads 13 to two sets of recording heads 10-12; 10 1 -12 1 , switches S being in their upper position. For playback, switches S are set to the position shown and the two sets of recorded data read out to flip-flops 20-22, 20 1 -22 1 , respectively, the outputs of these flip-flops being connected to parity checkers 26, 26 1 . If parity checker 26 1 indicates that the seond set of signals is incorrect, AND gates 30-32 are enabled to pass the output signals of the first set to output OR gates 40-42. If parity checker 26 indicates that the first set of signals is incorrect, AND gates 30 1 -32 1 are enabled to pass the output signals from flip-flops 20 1 -22 1 to the output gates 40-42. When the parity of both sets of signals is correct, AND gates 30-32 are enabled by a signal from parity checker 26 over line 27 and OR gate 29 to enable AND gates 30-32 to pass the signals of the first set to the output gates 40-42, the signals of the second set being inhibited by AND gates 30 1 -32 1 . When both parities are incorrect both sets of signals are supplied to the output gates 40-42, so that if the incorrect parities are due to drop-out in different channels in the two sets of signals, the correct output data may nevertheless be provided by the gates 40-42. In a modification (Fig. 3, not shown) both sets of signals are supplied to the output gates 40-42 when both parity checkers 26, 26 1 indicate correct parity so that when correct parity is indicated in one set of signals but two or more elements thereof are in error, the gates 40-42 may nevertheless provide a correct output.