AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Method and apparatus for floating point to fixed point conversion with compensation for lost precision

Abstract: A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit. A mask is generated by a lookup table according to the number of bits to be truncated. The mask supplies a logic 1 to one input of each such corresponding gate; the other input of each gate is driven by the bit to be truncated. If any such bit to be truncated is a one, then the output of the corresponding gate will be true. The outputs of all these AND gates or OR'ed together and the result stored in a latch; a SET latch then indicates the impending truncation of at least one 1. After the conversion the fractional portion of the destination register is checked to see if it is all zeros. If it is, and if the latch is also SET, then the least significant bit of the fractional portion of the destination register is forced to be understood as a 1 when the register is read.

Method of driving a gate line and gate drive circuit for performing the method

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

Abstract: With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Abstract: In this work, we propose a new Stepped Oxide Hetero-Material Trench (SOHMT) power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving (i) a good gate control on the channel charge and (ii) a lesser gate to drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high speed switching applications. In addition, the sandwiched gate with different work function gate materials modifies the electric field profile in the channel resulting in an improved breakdown voltage. Using two-dimensional simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench gate MOSFET.

Solid state image pickup device having a reliable photoelectric detection cell

Abstract: A solid state image pickup device is composed of basic cells each of which comprises a photodiode one terminal of which is grounded, a n-MOS transistor whose gate is connected to the other terminal of the photodiode and whose source is grounded and furthermore whose drain is connected to a load, a feedback capacitor and switching element for resetting both of which are connected between the drain and gate of the n-MOS transistor. As an advantage of such a configuration, the reduction of the sensitivity due to the junction capacitance of the photodiode can be suppressed, and furthermore accurate signal output voltages can be obtained even in the case where the amount of incident light changes during an integration period.