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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Patent
24 Aug 2006
TL;DR: In this paper, an ESD protection device includes an MOS transistor with a source region, drain region, and gate region, where a diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistors were in the active operating region.
Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

32 citations

Journal ArticleDOI
TL;DR: A new design for a threshold logic gate, based on clocked cross-coupled inverters, and the way to optimize the implementation of threshold functions using this gate are presented.
Abstract: In this paper we present both a new design for a threshold logic gate, based on clocked cross-coupled inverters, and the way to optimize the implementation of threshold functions using this gate. The main characteristics of the threshold gate are low power consumption (it does not consume static power) and high speed.

32 citations

Patent
01 Aug 2001
TL;DR: In this paper, a buried channel PMOS transistor for analog applications is integrated into a digital CMOS process by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the nwell and pwell regions for the digital PMOS process.
Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

32 citations

Journal ArticleDOI
TL;DR: This work fabricate and characterize a device (double-gate MoS2 FET with h-BN gate dielectrics and multi-layer graphene floating gate) in multiple operating conditions to demonstrate logic, memory, and synaptic applications and demonstrates this device as a versatile device, compatible to back-end-of-line integration, that could readily augment silicon technology.
Abstract: 2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable VT by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.

32 citations

Journal ArticleDOI
J. Hui1, F.-C. Hsu, J. Moll
TL;DR: In this article, a new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed, and a good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis.
Abstract: A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.

32 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372