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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Journal ArticleDOI
TL;DR: A mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay is developed.
Abstract: Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.

31 citations

Patent
10 Oct 2003
TL;DR: In this paper, the authors propose to use a mask or anti-spacer to decouple substrate and gate implantations in the logic transistors to achieve high-performance integrated circuits.
Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

31 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of the chiral character of carriers in graphene in different transport regimes including the Klein and band-to-band tunneling processes are analyzed. And the authors also predict the possible emergence of negative differential conductance and investigate its dependence on the BN-induced bandgap, temperature, and the gate insulator thickness.
Abstract: We study theoretically the different transport behaviors and the electrical characteristics of a top-gated graphene field-effect transistor where boron nitride is used as the substrate and gate insulator material, which makes the ballistic transport realistic. Our simulation model is based on the Green's function approach to solving a tight-binding Hamiltonian for graphene, self-consistently coupled with Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different transport regimes including the Klein and band-to-band tunneling processes. In particular, the Klein tunneling is shown to have an important role on the onset of the current saturation which is analyzed in detail as a function of the device parameters. Additionally, we predict the possible emergence of negative differential conductance and investigate its dependence on the BN-induced bandgap, the temperature, and the gate insulator thickness. Short-channel effects are evaluated from the analysis of transfer characteristics as a function of gate length and gate insulator thickness. They manifest through the shift of the Dirac point and the appearance of current oscillations at short gate length.

31 citations

Patent
06 Mar 1990
TL;DR: In this article, the rectifier restrains a photocurrent from reversely flowing between the drain and gate of an output FET in order to prevent the reverse flow of the photocurrent upon the conduction of the FET.
Abstract: A semiconductor relay circuit includes an output FET connected to a diode array. The diode array generates a photovoltaic output in response to a light signal from a light emitting element. Across the drain and gate of the FET is a series circuit of a semiconductor device and a rectifier is connected, the switching transistor is being made conductive upon receipt at the diode array of the light signal and forms a charge current path for an accumulated charge across the gate and source of the FET. The rectifier restrains a photocurrent from reversely flowing between the drain and gate of the FET. Turning-on and turning-off operations of the relay circuit can be thereby made both achievable at a higher speed, and the reverse flow of the photocurrent upon the conduction of the output FET can be prevented from occurring.

31 citations

Journal ArticleDOI
TL;DR: In this article, two qubits are encoded in zero and one-photon Fock states of two intracavity modes, and a four-level $\mathsf{N}$-type atomic ensemble trapped in a cavity mediates the conditional phase gate within a given interaction time.
Abstract: We propose a scheme for implementing a two-qubit quantum phase gate for intracavity fields. In the scheme, two qubits are encoded in zero- and one-photon Fock states of two intracavity modes, and a four-level $\mathsf{N}$-type atomic ensemble trapped in a cavity mediates the conditional phase gate within a given interaction time. We also discuss the influence of the atomic spontaneous emission and the decay of the cavity modes on the photon loss and gate fidelity, showing the scheme is within the current experiment technology.

31 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372