AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.

Split programmable logic array

Abstract: A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays. TABLE OF CONTENTS Subject Background of the Invention Summary of the Invention Brief Description of the Drawings Detailed Description of the Preferred Embodiment The System Block Diagram Microprocessor Unit Pin Designations Clock and Timing Signals System Timing The ROM The Stack Area The RAM Area Elimination of Race Conditions in the RAM The ALU and Control Time Slot End Predictor The CROM Bit Manipulation Scheme Data Pad Input/Output Precharged Data Line Driver Bus Control Test Circuitry Split PLA Control The S-Counter Details of Logic Blocks The MOS/LSI Chip The Chip Test Functions The Instruction Set

Depletion mode power MOSFET with refractory gate and method of making same

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Degenerate wavelength operation of an ultrafast all-optical AND gate using four wave mixing in a semiconductor laser amplifier

Abstract: A new, ultrafast, all-optical AND gate that operates on input signals at the same wavelength using four-wave mixing in a semiconductor laser amplifier is presented. Successful operation of the gate on 20 ps pulses modulated at 3 Gbit/s is descrihed. The device has applications in photonic networks operating at > 100 Gbit/s.

FATRAM-A Core Efficient Cut-Set Algorithm

Abstract: Many algorithms have been developed for determining minimal cut sets for logic models (in particular, fault trees). Although these methods are theoretically correct, computer implementation of these algorithms proves them less efficient than is desirable. This paper presents a new method for determining the minimal cut sets, which makes more efficient use of computer memory. The gates are resolved in a deterministic manner according to the following rules: 1) AND gates and OR gates with gate inputs are resolved; and 2) OR gates with only basic event inputs are resolved last. Other computer techniques provide increased efficiency for implementing this method. The FATRAM algorithm for finding minimal cut sets for fault trees does use computer core memory effectively. The use of stacks (last-in first-out arrays) for the AND and OR gates has also increased the efficiency of the program. The use of dynamic storage makes the program more flexible.