Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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Patent•
27 Dec 2006
TL;DR: In this paper, the authors proposed a TFT substrate, a reflective TFT, and a method of manufacturing the same which can enable stable operations for an extended period of time, prevent crosstalk, and remarkably reduce the manufacturing cost by reducing the number of steps in a manufacturing process.
Abstract: PROBLEM TO BE SOLVED: To propose a TFT substrate, a reflective TFT substrate, and a method of manufacturing the same which can enable stable operations for an extended period of time, prevent crosstalk, and remarkably reduce the manufacturing cost by reducing the number of steps in a manufacturing process. SOLUTION: A reflective TFT substrate 1a comprises a glass substrate 10, a gate electrode 23 and gate wiring 24 which are insulated by a gate insulating film 30 covering the top surfaces of the gate electrode 23 and the gate wiring 24 and an interlayer insulating film 50 covering the sides of the gate electrode 23 and the gate wiring 24, an n-type oxide semiconductor layer 40 formed on the gate insulating film 30 on the gate electrode 23, a reflective metal layer 60a formed on the n-type oxide semiconductor layer 40 via a channel portion 44, and a channel guard 500 for protecting the channel portion 44. COPYRIGHT: (C)2008,JPO&INPIT
31 citations
24 Oct 2008
TL;DR: In this article, the effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed, and the basic operational principles are effective on ZRAM cells with a gate length down to 12.5 nm.
Abstract: Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
31 citations
TL;DR: A dynamic programming approach is presented that solves the flight assignment problem in linear time with respect to the number of flights and gates for a fixed number of gates.
Abstract: This paper considers the problem of assigning flights to airport gates—a problem which is NP-hard in general. We focus on a special case in which the maximization of flight/gate preference scores is the only objective. We show that for a variable number of flights and gates, this problem is still NP-hard. For a fixed number of gates, we present a dynamic programming approach that solves the flight assignment problem in linear time with respect to the number of flights. Computational results using real life data from a major European airport prove the practical relevance of this approach.
31 citations
26 May 1997
TL;DR: In this article, a merged dual-gate power MOSFET was proposed to improve the light-load energy efficiency of high-speed lowvoltage DC/DC conversion by dynamically reducing input capacitance and gate drive losses during low-current load conditions.
Abstract: A merged dual-gate power MOSFET is described which greatly improves the light-load energy efficiency of high-speed (f>1 MHz) low-voltage DC/DC conversion by dynamically reducing input capacitance and gate drive losses during low-current load conditions. The W-switched MOSFET concept is experimentally verified using a TrenchFET employing a 30/spl times/ reduction in input capacitance during light load. Efficiency improvements better than 25% and a decade increase in useable load current were confirmed for a 1-cell Li ion to 5 V boost converter, without adversely affecting the converter's transient response. Various figure-of-merits for W-switched MOSFETs are also proposed to analyze the limits of W-switching.
31 citations
Patent•
10 Mar 2000TL;DR: In this paper, the gate insulating layer is modified to lower the dielectric constant in the gate to drain and gate to source overlap regions, relative to the more centrally located gate region between the source and drain.
Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the gate to drain and gate to source overlap capacitance of deep sub-micron CMOS devices, as an improved means of reducing device switching times. This is accomplished by customizing the gate insulating layer, such that the dielectric constant, K, is lower in the gate to drain and gate to source overlap regions, relative to the more centrally located gate region between the source and drain. This invention avoids the process control problems associated with using conventional post polysilicon gate oxidation as a means of lowering such overlap capacitance, particularly for the deep sub-micron regime.
31 citations