Topic
AND gate
About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.
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01 May 2014TL;DR: In this article, a driving circuit for a liquid crystal display device having a plurality of gate lines, data lines, and switch elements connected to the gate and data lines is described.
Abstract: A driving circuit for driving a liquid crystal display device having a plurality of gate lines, data lines and switch elements connected to the gate and data lines includes a data driver for applying a plurality of data signals to the date lines, a gate driver for applying a plurality of gate signals to the gate lines, a timing controller for providing a plurality of control signals to the data and gate drivers, a power supply for generating a power voltage, and a discharging circuit for applying a first signal and a second signal to the gate driver in accordance with the power voltage.
155 citations
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07 Oct 1998
TL;DR: In this paper, a threshold gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTed inputs remains greater than zero and less than the threshold value.
Abstract: An array includes a set of cells (21, 23, 25, 27, 29, 31). At least one of which includes a threshold gate (33, 35) having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.
155 citations
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09 Mar 2007
TL;DR: Evaluation and Logic Models: Using the Logic Model to provide Technical Assistance and Challenges in Developing Logic Models.
Abstract: List of Figures. Preface. 1. Evaluation and Logic Models. 2. The Uses of Logic Models. 3. The Components of a Logic Model. 4. The Connections in a Logic Model. 5. Developing Logic Models to Support Evaluation. 6. Developing Logic Models of Differing Complexity. 7. Using a Logic Model to Identify Evaluation Questions. 8. Using a Logic Model to Support Explanatory Evaluation. 9. Challenges in Developing Logic Models. 10. Developing Logic Models for Complex Projects. 11. Using Logic Models to Evaluate a Family of Projects. 12. Using the Logic Model to Provide Technical Assistance. Appendix: The Phases of an Evaluation. About the Author. Glossary. References.
155 citations
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02 Dec 1988
TL;DR: In this article, a random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle is presented, where decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals.
Abstract: A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.
151 citations
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TL;DR: The authors report the first demonstration of all-optical header recognition and self-routing of ultrafast packets with multibit addresses and a single optical AND gate recognises 6 bit ‘keyword’ codes, allowing self- routing of 100 Gbit/s packets.
Abstract: The authors report the first demonstration of all-optical header recognition and self-routing of ultrafast packets with multibit addresses. A single optical AND gate recognises 6 bit ‘keyword’ codes, allowing self-routing of 100 Gbit/s packets. [This Letter first appeared in print in 1995, issue 17, p.1475–1476, and has been reprinted because of the significance of the corrections.]
149 citations