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AND gate

About: AND gate is a research topic. Over the lifetime, 11860 publications have been published within this topic receiving 109726 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the gate and drain noise characteristics of an AlGaN/GaN high electron mobility transistor are investigated and a Hooge parameter (αH) ranging from 10−3 to 10−4 is extracted for drain current noise as a function of sheet carrier density.
Abstract: Room temperature low frequency noise characteristics of gate and drain currents of an AlGaN/GaN high electron mobility transistor are reported. A Hooge parameter (αH) ranging from 10−3 to 10−4 is extracted for drain current noise as a function of sheet carrier density. Gate current noise is simultaneously measured with drain noise both in the time and frequency domain. A weak correlation is seen between the drain and gate noise. Temporally unstable Lorentzian components on top of stable 1/fγ noise are observed in the gate noise spectra which also show up as random telegraph signal noise in the time domain. It is proposed that the gate Schottky contact is of high quality but that electrically unstable point defects in the AlGaN layer are the cause of Lorentzians and random telegraph switching noise.

30 citations

Journal ArticleDOI
TL;DR: In this paper, a model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift, which can be reduced to a level close to that of a boron-implanted gate by using an as-deposited amorphous silicon gate and a gate oxide process.
Abstract: Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

30 citations

Patent
05 Dec 2012
TL;DR: In this paper, a data analysis element including a plurality of memory cells is presented, where the memory cells analyze at least a portion of a data stream and output a result of the analysis.
Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

30 citations

Journal ArticleDOI
TL;DR: In this article, a two-dimensional simulator was used to demonstrate the trapping of hot electrons at gate edge model in GaN-based high-electron-mobility transistors.
Abstract: Using a two-dimensional simulator, the authors report on demonstration of trapping of hot electrons at gate edge model in GaN-based high-electron-mobility transistors. Dynamic picture of hot electrons under gate pulse voltage is discussed in detail. Trapped charges may accumulate under punch-off gate voltage at gate edge drain side, where the electric field significantly changes and gate-voltage-dependent strain is induced. Significant band barrier is formed at the gate edges causing a notable current collapse. Self-heating effect is one of the reasons for current collapse and gate lag.

30 citations

Patent
16 Apr 2004
TL;DR: In this article, a dual metal gate CMOS structure using an ultra thin aluminum nitride buffer layer between the metal gate and gate dielectric during processing was proposed to prevent the gate's oxide from being exposed in the metal etching process.
Abstract: A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AIN x ) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.

30 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202219
2021209
2020308
2019356
2018372